Texas Instruments VLYNQ Port manual Introduction, Purpose of the Peripheral, Features

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User's Guide

SPRUE36A – September 2007

VLYNQ Port

1 Introduction

1.1Purpose of the Peripheral

The VLYNQ™ communications interface port is a low pin count, high-speed, point-to-point serial interface in the TMS320DM644x Digital Media System-on-Chip (DMSoC) used for connecting to host processors and other VLYNQ-compatible devices. The VLYNQ port is a full-duplex serial bus where transmit and receive operations occur separately and simultaneously without interference.

VLYNQ enables the extension of an internal bus segment to one or more external physical devices. The external devices are mapped to local physical address space and appear as if they are on the internal bus of the DM644x DMSoC. The external devices must also have a VLYNQ interface.

VLYNQ uses a simple block code (8b/10b) packet format and supports in-band flow control so that no extra terminals are needed to indicate that overflow conditions might occur.

The VLYNQ module on the DM644x DMSoC serializes a write transaction to the remote/external device and transfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes the transaction on the other side.

The read transactions to the remote/external device follow the same process, but the remote device's VLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The read return data is finally deserialized and released to the device internal bus.

The external device can also initiate read and write transactions.

1.2Features

The general features of the VLYNQ port are:

∙Low pin count (10 pin interface, scalable to as low as 3 pins)

∙No tri-state signals

–All signals are dedicated and driven by only one device

–Necessary to allow support for high-speed PHYs

∙Scalable Performance

–Programmable frequency and 1 to 4 bits for TX and RX data

–Performance increases linearly as the data port width increases

∙Simple packet-based transfer protocol for memory-mapped access

–Write request/data packet

–Read request packet

–Read response data packet

–Interrupt request packet

∙Auto width negotiation

SPRUE36A –September 2007

VLYNQ Port

9

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid