Texas Instruments VLYNQ Port manual Signal Descriptions, Pin Multiplexing, Protocol Description

Page 12

www.ti.com

Peripheral Architecture

2.2Signal Descriptions

The VLYNQ module on the DM644x device is configurable for a 1 to 4 bit-wide RX/TX. Chip-level pin multiplexing registers control the configuration. See the pin multiplexing information in the device-specific data manual.

If the configured width does not match the number of transmit/receive lines that are available on the remote device, negotiation between the two VLYNQ devices automatically configures the width (see Section 2.7).

The VLYNQ interface signals are shown in Table 1.

Pin Name	Signal Name
VLYNQ_CLOCK	VLYNQ serial clock
VLYNQ_SCRUN	VLYNQ serial clock
	run request
	(Active low)

VLYNQ_RXD[0:3] VLYNQ receive data VLYNQ_TXD[0:3] VLYNQ transmit data

	Table 1. VLYNQ Port Pins
I/O	Description
I/O	The VLYNQ reference clock supports the internally or externally generated
	clock.
I/O	The VLYNQ serial clock run request allows remote requests for the VLYNQ
	serial clock to be turned off for system power management.
	Low: The request VLYNQ serial clock is active.
	High: The VLYNQ serial clock is requested to be high when all transactions are
	complete.
I	VLYNQ receive data is synchronous with the VLYNQ serial clock.
O	VLYNQ transmit data is synchronous with the VLYNQ serial clock.

2.3Pin Multiplexing

The VLYNQ signals share pins on the processor package with other processor functions. The VLYNQ module pins are not enabled at reset. In order to change the default function of device pins at reset, the pin multiplexing registers (PINMUXn) must be configured appropriately. See the pin multiplexing information in the device-specific data manual for more detailed information on the processor pin multiplexing and configuration registers.

2.4Protocol Description

VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet delineation and control.

Appendix A provides general information on 8b/10b coding definitions and their implementation within the VLYNQ module in the DM644x device.

12

VLYNQ Port

SPRUE36A –September 2007

Submit Documentation Feedback

Image 12

Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlSignal Descriptions Vlynq Port PinsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Serial Interface Width Configuration InitializationAuto-Negotiation Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Registers Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersAppendix a Vlynq Protocol Specifications Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceTable B-1. Scaling Factors Burst Size in 32-bit words Data BytesBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid