Texas Instruments VLYNQ Port manual List of Tables

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	List of Tables
1	VLYNQ Port Pins	12
2	Serial Interface Width	16
3	Address Translation Example (Single Mapped Region)	18
4	Address Translation Example (Single Mapped Region)	19
5	VLYNQ Register Address Space	25
6	VLYNQ Port Controller Registers	25
7	Revision Register (REVID) Field Descriptions	26
8	Control Register (CTRL) Field Descriptions	27
9	Status Register (STAT) Field Descriptions	29
10	Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions	31
11	Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions	31
12	Interrupt Pending/Set Register (INTPENDSET) Field Descriptions	32
13	Interrupt Pointer Register (INTPTR) Field Descriptions	32
14	Address Map Register (XAM) Field Descriptions	33
15	Receive Address Map Size 1 Register (RAMS1) Field Descriptions	34
16	Receive Address Map Offset 1 Register (RAMO1) Field Descriptions	34
17	Receive Address Map Size 2 Register (RAMS2) Field Descriptions	35
18	Receive Address Map Offset 2 Register (RAMO2) Field Descriptions	35
19	Receive Address Map Size 3 Register (RAMS3) Field Descriptions	36
20	Receive Address Map Offset 3 Register (RAMO3) Field Descriptions	36
21	Receive Address Map Size 4 Register (RAMS4) Field Descriptions	37
22	Receive Address Map Offset 4 Register (RAMO4) Field Descriptions	37
23	Chip Version Register (CHIPVER) Field Descriptions	38
24	Auto Negotiation Register (AUTNGO) Field Descriptions	38
25	VLYNQ Port Remote Controller Registers	39
A-1	Special 8b/10b Code Groups	40
A-2	Supported Ordered Sets	40
A-3	Packet Format (10-bit Symbol Representation) Description	42
B-1	Scaling Factors	46
B-2	Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)	46
B-3	Relative Performance with Various Latencies	47
C-1	Document Revision History	48

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List of Tables

SPRUE36A –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlPin Multiplexing Signal DescriptionsVlynq Port Pins Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address SizeRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersSupported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceBurst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid