Texas Instruments VLYNQ Port manual Transmit Address Map Register XAM, Txadrmap

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VLYNQ Port Registers

3.8Transmit Address Map Register (XAM)

The transmit address map register (XAM) is used to translate transmit packet addresses to remote device configuration bus addresses. The XAM is shown in Figure 16 and described in Table 14.

Figure 16. Transmit Address Map Register (XAM)

31

2

1

0

TXADRMAP

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 14. Address Map Register (XAM) Field Descriptions

Bit

Field

Value

Description

31-2

TXADRMAP

0-3FFF FFFFh

This field is subtracted from the slave configuration bus address [25:0] to obtain the zero

 

 

 

relative transmit packet address. This field should be programmed with a value of 0 (reset

 

 

 

value).

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

SPRUE36A –September 2007

VLYNQ Port

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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