Texas Instruments VLYNQ Port manual DM644x Vlynq Module, Remote Vlynq Module

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Peripheral Architecture

DM644x VLYNQ Module:

	0C00 : 0054h	Initial address at the slave configuration bus
	0000 : 0054h	Initial address [25:0] at the slave configuration bus interface
subtract	0000 : 0000h	TX address map register (there is no need to change the reset value of the
		DM644x device for this register)
	0000 : 0054h
Remote VLYNQ Module:
	0000 : 0054h	Initial address from the RX serial interface
compare	0000 : 0100h	RX address map size 1 register
	0000 : 0054h
add	0800 : 0000h	RX address map offset 1 register
	0800 : 0054h	Translated address to remote device

The local address 0C00 : 0054h (or 0000 0054h) was translated to 0800 : 0054h on the remote VLYNQ device in Table 4.

Table 4 illustrates the address map register configuration when the DM644x device is receiving data from the remote device.

Table 4. Address Translation Example (Single Mapped Region)

Register	DM644x VLYNQ Module	Remote VLYNQ Module
TX Address Map	Do not care	0400 : 0000h
RX Address Map Size 1	0000 : 0100h	Do not care
RX Address Map Offset 1	0200 : 0000h	Do not care
RX Address Map Size 2	0000 : 0100h	Do not care
RX Address Map Offset 2	8200 : 0000h	Do not care

Remote VLYNQ Module:
	0400 : 0154h Initial address at the slave configuration bus for the remote device
subtract	0400 : 0000h	TX address map register
	0000 : 0154h Translated address to remote device via serial interface
DM644x VLYNQ Module:
	0000 : 0154h Initial address from the RX serial interface
compare	0000 : 0100h	RX address map size 1 register
	0000 : 0154h The RX packet address is greater than the value in the RX address map size 1
		register
compare	0000 : 0200h	RX address map size 1 register + RX address map size 2
		Since the RX packet address < the RX address map size 1 register +
		RX address map size 2 register
add	8200 : 0000h	RX address map offset 2 register
subtract	0000 : 0100h	RX address map size 1 register
	8200 : 0054h Translated address to DM644x device
SPRUE36A –September 2007		VLYNQ Port	19

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureProtocol Description Signal DescriptionsVlynq Port Pins Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-NegotiationAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramDMA Event Support Serial Bus Error InterruptsRemote Interrupts Emulation Considerations Power ManagementBlock Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller RegistersBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersTable A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceTable C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid