Texas Instruments VLYNQ Port manual Address Translation Example Single Mapped Region

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Peripheral Architecture

Figure 7. Example Address Memory Map

 

Remote

DMxxx￿device￿(local)

VLYNQ￿device

 

0000:0000

 

Map￿region￿1

0400:0000

 

(0C00:0000￿on￿CONFIG￿bus)

 

Map￿region￿1

03FF:FFFF

0400:0000

 

 

Map￿region￿2

07FF:FFFF

0400:00FF

0800:0000

 

Map￿region￿2

 

0800:00FF

0500:0000

0800:0100

 

Map￿region￿3

Map￿region￿3

0801:00FF

0500:FFFF

0801:0100

 

Map￿region￿4

 

 

0B00:0000

0841:00FF

Map￿region￿4

 

 

0B3F:FFFF

The following shows an example illustrating the address translation used in each VLYNQ module. Address bits [31:26] are not used for address translation to remote devices on the DM644x device.

Table 3 illustrates address map register configuration when the DM644x device is transmitting data to the remote device.

Table 3. Address Translation Example (Single Mapped Region)

Register

DM644x VLYNQ Module

Remote VLYNQ Module

TX Address Map

0000 : 0000h

Do not care

RX Address Map Size 1

Do not care

0000 : 0100h

RX Address Map Offset 1

Do not care

0800 : 0000h

18

VLYNQ Port

SPRUE36A –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlPin Multiplexing Signal DescriptionsVlynq Port Pins Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address SizeRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersSupported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceBurst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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