Texas Instruments VLYNQ Port manual Power Management, Emulation Considerations

Page 24

www.ti.com

Peripheral Architecture

2.14 Power Management

The VLYNQ module can be placed in reduced-power modes to conserve power during periods of low activity. The power management of the peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management of all of the peripherals on the processor.

The power conservation modes that are available via the PSC are:

∙Idle/Disabled state : Idle/disabled state stops the clocks from going to the peripheral and prevents all of the register accesses. After re-enabling the peripheral from its idle state, all registers prior to setting in the disabled state are restored and data transmission proceeds. Re-initialization is not required.

∙Synchronized reset : The synchronized reset state is similar to the power-on reset (POR) state. When the processor is turned on, reset to the peripheral is asserted, then clocks to the peripheral are gated. Registers reset to their default values. When powering-up after a synchronized reset, all of the VLYNQ module registers must be reconfigured and the link must be re-established before data transmission.

For more detailed information on power management procedures using the PSC, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14).

If the serial clock is internally sourced, you can use the CLKDIV bit in the VLYNQ control register (CTRL) to divide the serial clock down. This saves normal mode operation power consumption (at the expense of reduced performance).

Additionally, the module provides the capability of auto-idling the serial clock domain (disable the VLYNQ CLK) when the serial clock is sourced from the DM644x device and the VLYNQ SCRUN pin is connected to the remote device. This allows power savings when there is no activity on the serial interface.

Note: There is no support for external wake-up for the VLYNQ module on the DM644x device. If the VLYNQ module on the DM644x device has been disabled via the PSC, then even though serial activity requests can be indicated from the remote VLYNQ device via the VLYNQ SCRUN pin, it does not allow the serial clock (VLYNQ CLK) to be sourced until the VLYNQ module is re-enabled via the PSC.

This can be configured by enabling the power management enable (PMEN) bit in the VLYNQ control registers (CTRL, 0 = disable, 1 = enable) . This bit should only be set if the SCRUN pin is connected to the remote VLYNQ device.

The SCRUN pin is a bi-directional pin which is driven low whenever there is serial activity on the local or remote VLYNQ interface.

2.15 Emulation Considerations

During debug, the ARM CPU may be halted for single stepping, bench marking, profiling, or other debug uses using the emulator. VLYNQ does not support emulation halts/suspend operation. VLYNQ operations continue during emulation halt/suspend.

24

VLYNQ Port

SPRUE36A –September 2007

Page 23 Page 25
Image 24
Page 23 Page 25
Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlSignal Descriptions Vlynq Port PinsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Serial Interface Width Configuration InitializationAuto-Negotiation Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Registers Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersAppendix a Vlynq Protocol Specifications Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceTable B-1. Scaling Factors Burst Size in 32-bit words Data BytesBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
Top Page Image Contents