Texas Instruments VLYNQ Port manual Remote Configuration Registers

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Remote Configuration Registers

4Remote Configuration Registers

The remote configuration registers listed in Table 25 are the same registers as previously described, but they are for the remote VLYNQ device.

Note: Before attempting to access the remote registers (offsets 80h through C0h) , you must ensure that a link is established with the remote device. Poll the LINK bit in the VLYNQ status register (STAT) to do this.

It is not necessary to configure the address translation registers to access the remote device'smemory-mapped registers after the link has been established.

Depending on the version and chip specific implementation, the VLYNQ module on the remote device might have additional registers or different reset values. Refer to the remote device data sheet for a precise description of the VLYNQ registers that exist in the remote device.

	Table 25. VLYNQ Port Remote Controller Registers
Offset	Acronym	Register Description
80h	RREVID	Remote Revision Register
84h	RCTRL	Remote Control Register
88h	RSTAT	Remote Status Register
8Ch	RINTPRI	Remote Interrupt Priority Vector Status/Clear Register
90h	RINTSTATCLR	Remote Interrupt Status/Clear Register
94h	RINTPENDSET	Remote Interrupt Pending/Set Register
98h	RINTPTR	Remote Interrupt Pointer Register
9Ch	RXAM	Remote Transmit Address Map Register
A0h	RRAMS1	Remote Receive Address Map Size 1 Register
A4h	RRAMO1	Remote Receive Address Map Offset 1 Register
A8h	RRAMS2	Remote Receive Address Map Size 2 Register
ACh	RRAMO2	Remote Receive Address Map Offset 2 Register
B0h	RRAMS3	Remote Receive Address Map Size 3 Register
B4h	RRAMO3	Remote Receive Address Map Offset 3 Register
B8h	RRAMS4	Remote Receive Address Map Size 4 Register
BCh	RRAMO4	Remote Receive Address Map Offset 4 Register
C0h	RCHIPVER	Remote Chip Version Register
C4h	RAUTNGO	Remote Auto Negotiation Register
C8h	RMANNGO	Remote Manual Negotiation Register
CCh	RNGOSTAT	Remote Negotiation Status Register
E0h	RINTVEC0	Remote Interrupt Vector 3-0 Register
E4h	RINTVEC1	Remote Interrupt Vector 7-4 Register

SPRUE36A –September 2007	VLYNQ Port	39
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureProtocol Description Signal DescriptionsVlynq Port Pins Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-NegotiationAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Emulation Considerations Power ManagementBlock Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller RegistersBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersTable A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid