Texas Instruments VLYNQ Port manual Vlynq Port Registers, Vlynq Register Address Space

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VLYNQ Port Registers

3VLYNQ Port Registers

Table 5 describes the address space for the VLYNQ registers and memory.

Table 5. VLYNQ Register Address Space

Block Name	Start Address	End Address	Size
VLYNQ Control Registers	01E0 1000h	01E0 11FFh	512 bytes
Reserved	01E0 1200h	01E0 1FFFh	-
VLYNQ Remote Memory Map	0C00 0000h	0CFF FFFFh	64 Mbytes

Table 6 lists the memory-mapped registers for the VLYNQ port controller. See the device-specific data manual for the memory address of these registers.

The first 128 bytes map to the VLYNQ configuration registers that are maintained by the local (device) VLYNQ register control module while the second 128 bytes map to the remote configuration registers that are physically located in the remote device linked by the VLYNQ serial interface. Any access to the second set of registers causes VLYNQ to issue a read or write VLYNQ packet to be transmitted and only completes if a link is established between the two devices.

Table 6. VLYNQ Port Controller Registers

Offset	Acronym	Register Description	Section
0h	REVID	Revision Register	Section 3.1
4h	CTRL	Control Register	Section 3.2
8h	STAT	Status Register	Section 3.3
Ch	INTPRI	Interrupt Priority Vector Status/Clear Register	Section 3.4
10h	INTSTATCLR	Interrupt Status/Clear Register	Section 3.5
14h	INTPENDSET	Interrupt Pending/Set Register	Section 3.6
18h	INTPTR	Interrupt Pointer Register	Section 3.7
1Ch	XAM	Transmit Address Map Register	Section 3.8
20h	RAMS1	Receive Address Map Size 1 Register	Section 3.9
24h	RAMO1	Receive Address Map Offset 1 Register	Section 3.10
28h	RAMS2	Receive Address Map Size 2 Register	Section 3.11
2Ch	RAMO2	Receive Address Map Offset 2 Register	Section 3.12
30h	RAMS3	Receive Address Map Size 3 Register	Section 3.13
34h	RAMO3	Receive Address Map Offset 3 Register	Section 3.14
38h	RAMS4	Receive Address Map Size 4 Register	Section 3.15
3Ch	RAMO4	Receive Address Map Offset 4 Register	Section 3.16
40h	CHIPVER	Chip Version Register	Section 3.17
44h	AUTNGO	Auto Negotiation Register	Section 3.18

SPRUE36A –September 2007	VLYNQ Port	25
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramDMA Event Support Serial Bus Error InterruptsRemote Interrupts Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceTable C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid