Texas Instruments VLYNQ Port Receive Address Map Size 3 Register RAMS3, RXADRSIZE3, RXADROFFSET3

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VLYNQ Port Registers

3.13 Receive Address Map Size 3 Register (RAMS3)

The receive address map size 3 register (RAMS3) is used to identify the intended destination of inbound serial packets. The RAMS3 is shown in Figure 21 and described in Table 19.

Figure 21. Receive Address Map Size 3 Register (RAMS3)

31

2

1

0

RXADRSIZE3

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 19. Receive Address Map Size 3 Register (RAMS3) Field Descriptions

Bit

Field

Value

Description

31-2

RXADRSIZE3

0-3FFF FFFFh

The RXADRSIZE3 field is used to determine if receive packets are destined for the third of

 

 

 

four mapped address regions. RXADRSIZE3 is compared with the address contained in the

 

 

 

receive packet. If the receive packet address is less than the value in RXADRSIZE3, the

 

 

 

packet address is added to the receive address map offset 3 register (RAMO3) to obtain the

 

 

 

translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

3.14 Receive Address Map Offset 3 Register (RAMO3)

The receive address map offset 3 register (RAMO3) is used with the receive address map size 3 register (RAMS3) to translate receive packet addresses to local device configuration bus addresses. The RAMO3 is shown in Figure 22 and described in Table 20.

Figure 22. Receive Address Map Offset 3 Register (RAMO3)

31

2

1

0

RXADROFFSET3

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 20. Receive Address Map Offset 3 Register (RAMO3) Field Descriptions

Bit

Field

Value

Description

31-2

RXADROFFSET3

0-3FFF FFFFh

The RXADROFFSET3 field is used with the receive address map size 3 register (RAMS3)

 

 

 

to determine the translated address for serial data. If the receive packet address is less

 

 

 

than the value in RAMS3, the packet address is added to the contents of this register to

 

 

 

obtain the translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

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VLYNQ Port

SPRUE36A –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlSignal Descriptions Vlynq Port PinsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Serial Interface Width Configuration InitializationAuto-Negotiation Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Registers Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersAppendix a Vlynq Protocol Specifications Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceTable B-1. Scaling Factors Burst Size in 32-bit words Data BytesBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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