Texas Instruments TMS320DM643x manual Overview, Clock Domains, Core Domains, Subsystem

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Overview

4.1Overview

The DM643x DMP requires one primary reference clock. The primary reference clock can be either crystal input or driven by external oscillators. A 27 MHZ crystal at the MXI/CLKIN pin is recommended for the system PLLs, which generate the clocks for the DSP, peripherals, DMA, and imaging peripherals. The recommended 27 MHZ input enables you to use the video DACs to drive NTSC/PAL television signals at the proper frequencies.

For detailed specifications on clock frequency and voltage requirements, see the device-specific data manual.

There are two clocking modes:

∙PLL Bypass Mode - power saving (device defaults to this mode)

∙PLL Mode - PLL multiplies input clock up to the desired operating frequency

The clock of the major chip subsystems must be programmed to operate at fixed ratios of the primary system/DSP clock frequency within each mode, as shown in Table 4-1. The DM643x DMP clocking architecture is shown in Figure 4-1.

Table 4-1. System Clock Modes and Fixed Ratios for Core Clock Domains

Subsystem

Core Clock Domain

Fixed Ratio vs. DSP frequency

DSP

CLKDIV1

1:1

EDMA

CLKDIV3

1:3

VPSS

 

 

Peripherals (CLKDIV3 domain)

CLKDIV3

1:3

Peripherals (CLKDIV6 domain)

CLKDIV6

1:6

4.2Clock Domains

4.2.1 Core Domains

The core domains refer to the clock domains for all of the internal processing elements of the DM643x DMP, such as the DSP/EDMA/peripherals, etc. All internal communications between DSP and modules operate at core domain clock frequencies. All of the core clock domains are synchronous to each other, come from a single PLL (PLL1), have aligned clock edges, and have fixed divide by ratio requirements, as shown in Table 4-1and Figure 4-1. It is user's responsibility to ensure the fixed divide ratios between these core clock domains are achieved.

The DSP is in the CLKDIV1 domain and receives the PLL1 frequency directly (PLLDIV1 of PLL controller 1 (PLLC1) set to divide by 1), or receives the divided-down PLL1 frequency (PLLDIV1 of PLLC1 set to divide by 2, 3, etc.). The DSP has internal clock dividers that it uses to create the DSP ÷ 3 clock frequency to communicate with other components on-chip.

Modules in the CLKDIV3 domain (for example, EDMA, VPSS, CLKDIV3 domain peripherals) must run at 1/3 the DSP frequency.

Modules in the CLKDIV6 domain (for example, CLKDIV6 domain peripherals) must run at 1/6 the DSP frequency.

Modules in the CLKIN domain (for example, UART, Timer, I2C, PWM, HECC) run at the MXI/CLKIN frequency, asynchronous to the DSP. There is no fixed ratio requirement between these peripherals frequencies and the DSP frequency.

Refer to device-specific data manual for the core clock domain for each peripheral.

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Device Clocking

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Notational Conventions Read This FirstAbout This Manual Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaPower-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewExternal Memory Memory MapDSP Internal Memory L1P, L1D, L2 Internal PeripheralsExternal Memory Interface Memory Interfaces Overview1 DDR2 External Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsCore Domains OverviewClock Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Voltage Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlSystem PLLC1 Output Clocks Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPllout PLL2 ControlDDR PLLC2 Output Clocks Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Base Address End Address Size PLL and Reset Controller ListPLL and Reset Controller Registers PLL Controller RegistersPeripheral ID Register PID Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 D1END2EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden Goset PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat StableALN3 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN2Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 Obsen Auxen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions ObsenBpon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Obson AuxonSYS3ON SYS2ON SYS1ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module StatesExecuting State Transitions Local ResetPower Domain State Transitions Module State TransitionsPSC Interrupts IcePick Emulation CommandsIcePick Emulation Support in the PSC Interrupt EventsLocal Reset Emulation Events Interrupt RegistersModule State Emulation Events PSC Registers Power and Sleep Controller PSC RegistersInterrupt Handling Offset Register DescriptionPeripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 State Power Domain Status 0 Register PDSTAT0Pordone POR PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsEmuihbie Emurstie Lrst Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewModule Clock ON/OFF PLL Bypass and Power DownClock Management Module Clock Frequency ScalingDSP Module Clock ON/OFF DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock on3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Identification Device ConfigurationDevice Boot Configuration Status Pin Multiplexing Control3 DDR2 VTP Control Timer ControlVpss Clock and DAC Control HPI ControlTMS320DM643x DMP Master IDs Bandwidth ManagementBus Master DMA Priority Control DSP CFGTMS320DM643x DMP Default Master Priorities Edma Transfer Controller ConfigurationBoot Control DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.2 Reset10.1 10.3Reset Types Reset PinsDevice Configurations at Reset Type Initiator EffectDSP Module Reset DSP ResetDSP Local Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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