Texas Instruments TMS320DM643x DSP Sleep Mode Management, DSP Sleep Modes, DSP Module Clock on

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DSP Sleep Mode Management

7.4DSP Sleep Mode Management

The C64x+ DSP supports sleep mode management to reduce power:

∙DSP clock can be completely shut off

∙C64x+ Megamodule can be put in sleep mode

– C64x+ CPU can be put in sleep mode

On the DM643x DMP, sleep mode for the DSP internal memories (L1P, L1D, L2) is not supported.

7.4.1 DSP Sleep Modes

The C64x+ Megamodule of the DSP subsystem includes a power-down controller (PDC) that controls the power-down of the C64x+ Megamodule components. Refer to Section 2.4.2 and the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more details on the PDC.

7.4.2 DSP Module Clock ON/OFF

As discussed in Section 7.4.1, the C64x+ Megamodule can clock gate its own components to save power. Additional power saving can be achieved by stopping the clock source to the C64x+ Megamodule by programming the power and sleep controller (PSC) to place the C64x+ Megamodule in Disable state. The C64x+ DSP cannot perform this programming task on its own, because the C64x+ DSP will not be able to complete the PSC programming sequence if the C64x+ DSP clock source is gated in the middle of the process. If stopping the clock source to the C64x+ DSP is desired for additional power saving, an external host is responsible for programming the PSC (for example, via HPI, PCI interfaces) to disable the C64x+ Megamodule. Similarly, in that case the external host is responsible for programming the PSC to enable the C64x+ Megamodule.

7.4.2.1DSP Module Clock ON

In the clock Enable state, the DSP’s module clock is enabled while DSP module reset is de-asserted. This is the state for normal DSP run-time. DSP defaults to Enable state, therefore this DSP Module Clock ON process is typically not needed. This process is only required to wake up the DSP after an external host puts the DSP in Disable state (Section 7.4.2.2).

∙Host: Enable clocks to the DSP.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition.

–Set the NEXT bit in MDCTL39 to 3h to prepare the DSP module for an enable transition.

–Set the GO[0] bit in PTCMD to 1 to initiate the state transition.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0.

–Wait for the STATE bit in MDSTAT39 to change to 3h. The module is only safely in the new state after the STATE bit in MDSTAT39 changes to reflect the new state.

∙Host: Wake the DSP.

–If transitioning from the disable state, trigger a DSP interrupt that has previously been configured as a wake-up interrupt.

Note: This step only applies if you are transitioning from the disable state. If previously in the disable state, a wake-up interrupt must be triggered in order to wake the DSP. This example assumes that the DSP enabled this interrupt before entering its IDLE state. If previously in the software reset disable or synchronous reset state, it is not necessary to wake the DSP because these states assert the DSP module reset. See Chapter 10 for information on the software reset disable and synchronous reset states. See the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on DSP interrupts.

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SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Read This First About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaInterrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewMemory Map DSP Internal Memory L1P, L1D, L2External Memory Internal PeripheralsMemory Interfaces Overview 1 DDR2 External Memory InterfaceExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsOverview Clock DomainsCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Frequency Flexibility Example PLL1 Frequencies and Dividers 27 MHZ Clock InputCore Voltage Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlDevice Clock Generation Steps for Changing PLL1/Core Domain FrequencySystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPLL2 Control DDR PLLC2 Output ClocksPllout Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller List PLL and Reset Controller RegistersPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Reset Type Status Register Rstype Field DescriptionsPeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm PLL Controller Divider 1 Register PLLDIV1PLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 2 Register PLLDIV2 PLL Controller Divider 3 Register PLLDIV3D2EN D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions PLL Controller Command Register Pllcmd PLL Controller Status Register PllstatGoset StablePLL Controller Clock Align Control Register Alnctl ALN2 ALN1ALN3 ALN2SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 Clock Enable Control Register Cken 18. Clock Enable Control Register Cken Field DescriptionsObsen Auxen ObsenClock Status Register Ckstat 19. Clock Status Register Ckstat Field DescriptionsBpon Obson AuxonSysclk Status Register Systat 20. Sysclk Status Register Systat Field DescriptionsSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Power Domain and Module States Power Domain StatesModule States Module StatesLocal Reset Power Domain State TransitionsExecuting State Transitions Module State TransitionsIcePick Emulation Commands IcePick Emulation Support in the PSCPSC Interrupts Interrupt EventsModule State Emulation Events Local Reset Emulation EventsInterrupt Registers Power and Sleep Controller PSC Registers Interrupt HandlingPSC Registers Offset Register DescriptionInterrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Pending Register 1 MERRPR1 Module Error Clear Register 1 MERRCR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsGOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat Power Domain Status 0 Register PDSTAT0 Pordone PORState PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsModule Control n Register MDCTLn 15. Module Control n Register MDCTLn Field DescriptionsEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewPLL Bypass and Power Down Clock ManagementModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Mode Management DSP Sleep ModesDSP Module Clock ON/OFF DSP Module Clock onDSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Configuration Device Boot Configuration StatusDevice Identification Pin Multiplexing ControlTimer Control Vpss Clock and DAC Control3 DDR2 VTP Control HPI ControlBandwidth Management Bus Master DMA Priority ControlTMS320DM643x DMP Master IDs DSP CFGEdma Transfer Controller Configuration Boot ControlTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback Reset 10.110.2 10.3Reset Pins Device Configurations at ResetReset Types Type Initiator EffectDSP Reset DSP Local ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP
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