Texas Instruments TMS320DM643x manual PLL2 Control, DDR PLLC2 Output Clocks, Pllout

Page 43

www.ti.com

PLL2 Control

5.3PLL2 Control

PLL2 provides the clock from which the DDR2 memory controller and optional VPBE clocks are derived. The DDR PLL controller 2 (PLLC2) controls PLL2, which accepts the clock from the oscillator and also generates the various frequency clocks needed. Figure 5-2shows the customization of PLL2 in the DM643x DMP. The PLL2 clocks are distributed to the device as follows:

∙SYSCLK1: DDR2 PHY

∙SYSCLK2: VPSS

∙SYSCLKBP: DDR2 VTP

PLL2 supplies the DDR2 memory controller clock. Software controls the PLL2 operation through the DDR PLL controller 2 (PLLC2) registers. The registers used in PLLC2 are listed in Section 5.4. The PLL2 multiplier is controlled by the PLLM bit of the PLL multiplier control register (PLLM). The PLL2 multiplier may be modified by software (for example, to tune the DDR interface for best performance).

The PLL2 output clock must be divided-down to the DDR operating range using the SYSCLK1 divider.

At power-up, PLL2 is powered-down and disabled, and must be powered-up by software through the PLL2 PLLPWRDN bit in the PLL control register (PLLCTL). By default, the system operates in bypass mode and the DDR clock is provided directly from the input reference clock. Once the PLL is powered-up and locked, software can switch the device to PLL mode operation by setting the PLLEN bit in PLLCTL to 1.

Figure 5-2. PLL2 Structure in the TMS320DM643x DMP

 

CLKMODE

 

 

 

PLLEN

CLKIN

1

PLLOUT

 

 

PLL

1

OSCIN

0

 

 

 

0

 

PLLM

 

 

 

BPDIV

PLLDIV2 (/10)

PLLDIV1 (/2)

PLL2_SYSCLK2 (VPSS−VPBE)

PLL2_SYSCLK1 (DDR2 PHY)

PLL2_SYSCLKBP (DDR2 VTP)

5.3.1 Device Clock Generation

PLLC2 generates two clocks from the PLL2 output clock for use by the DDR2 memory controller and VPSS modules. These are summarized in Table 5-2.

Table 5-2. DDR PLLC2 Output Clocks

Output Clock

Used by

Default Divider

SYSCLK2

VPSS

/10

SYSCLK1

DDR Phy

/2

SYSCLKBP

DDR VTP Controller

/2

The SYSCLK1 output clock divider value defaults to /2. Assuming a 27 MHZ MXI/CLKIN and the PLL2 default multiplier of ×20, this results in a 270 MHZ DDR Phy clock (135 MHZ DDR2). It can be modified by software (RATIO bit in PLLDIV1) in combination with other PLL multipliers to achieve the desired DDR clock rate. The SYSCLK2 divider is programmable to allow a 54 MHZ output to be generated from any even-multiple PLL output frequency for use by the VPSS.

SPRU978E–March 2008

PLL Controller

43

Page 42 Page 44
Image 43
Page 42 Page 44
Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Read This FirstAbout This Manual Notational ConventionsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Introduction Block DiagramPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCInternal Peripherals Power-Down Controller PDCInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryInternal Peripherals Memory MapDSP Internal Memory L1P, L1D, L2 External MemoryAsynchronous Emif Interface Memory Interfaces Overview1 DDR2 External Memory Interface External Memory InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingSystem Clock Modes and Fixed Ratios for Core Clock Domains OverviewClock Domains Core DomainsHecc Overall Clocking DiagramDivider Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core VoltageExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModulePLLC1 Output Clock Used by Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency System PLLC1 Output ClocksInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersOutput Clock Used by PLL2 ControlDDR PLLC2 Output Clocks PlloutSteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL Controller Registers PLL and Reset Controller ListPLL and Reset Controller Registers PLL and Reset Controller Base Address End Address SizePeripheral ID Register PID Field Descriptions Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PIDPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlD1EN PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register Pllm Field DescriptionsD3EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D2ENOD1EN Oscillator Divider 1 Register OSCDIV113. Bypass Divider Register Bpdiv Field Descriptions Bypass Divider Register BpdivBpden Stable PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat GosetALN2 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN3SYS3 SYS2 SYS1 Plldiv Ratio Change Status Register DchangeSYS3 Obsen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions Obsen AuxenObson Auxon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions BponSYS3ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ON SYS2ON SYS1ONPower and Sleep Controller Power and Sleep Controller PSC Integration DM643x DMP Default Module Configuration Power Domain and Module TopologyNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module StatesModule State Transitions Local ResetPower Domain State Transitions Executing State TransitionsInterrupt Events IcePick Emulation CommandsIcePick Emulation Support in the PSC PSC InterruptsInterrupt Registers Local Reset Emulation EventsModule State Emulation Events Offset Register Description Power and Sleep Controller PSC RegistersInterrupt Handling PSC RegistersInterrupt Evaluation Register Inteval Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1 Field DescriptionsPower Domain Transition Status Register Ptstat Power Domain Transition Command Register PtcmdGOSTAT0 Pordone Power Domain Status 0 Register PDSTAT0Pordone POR StateNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATnEmuihbie Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions Emuihbie Emurstie LrstSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionModule Clock Frequency Scaling PLL Bypass and Power DownClock Management Module Clock ON/OFFDSP Module Clock on DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock ON/OFFVideo DAC Power Down 3.3 V I/O Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Pin Multiplexing Control Device ConfigurationDevice Boot Configuration Status Device IdentificationHPI Control Timer ControlVpss Clock and DAC Control 3 DDR2 VTP ControlDSP CFG Bandwidth ManagementBus Master DMA Priority Control TMS320DM643x DMP Master IDsDSP DMA DSP CFG Emac Edma Transfer Controller ConfigurationBoot Control TMS320DM643x DMP Default Master PrioritiesSubmit Documentation Feedback 10.3 Reset10.1 10.2Type Initiator Effect Reset PinsDevice Configurations at Reset Reset TypesSoftware Reset Disable SwRstDisable DSP ResetDSP Local Reset DSP Module ResetSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Table A-1. Document Revision History Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid
Top Page Image Contents