Texas Instruments TMS320DM643x manual Memory Controllers, 1 L1P Controller

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Memory Controllers

2.3Memory Controllers

The C64x+ Megamodule implements a two-level internal cache-based memory architecture with external memory support. Level 1 memory is split into separate program memory (L1P memory) and data memory (L1D memory). Figure 2-2shows a diagram of the memory architecture. L1P and L1D are configurable as part L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to the CPU without stalls. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chip memory) and L2 cache for caching external memory locations.

The following controllers manage RAM/cache configuration and cache data paths:

∙L1P controller

∙L1D controller

∙L2 controller

∙External memory controller (EMC)

The internal direct memory access (IDMA) controller manages DMA among the L1P, L1D, and L2 memories.

This section briefly describes the cache and DMA controllers. For detailed information about each of these controllers, see the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871).

Note: The C64x+ Megamodule includes the memory controllers; however, the physical L1P, L1D, and L2 memories are not part of the megamodule, even though they reside in the DSP subsystem. Thus, the physical memories are described separately because the C64x+ Megamodule supports a variety of memory configurations. Refer to Section 3.1 for more information on the L1P, L1D, and L2 memory configuration specific to the DM643x DMP.

2.3.1 L1P Controller

The L1P controller is the hardware interface between level 1 program memory (L1P memory) and the other components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1P controller responds to instruction fetch requests from the C64x+ CPU and manages transfer operations between L1P memory and the L2 controller and between L1P memory and the EMC.

Refer to the device-specific data manual for the amount of L1P memory on the device. The L1P controller has a register interface that allows you to configure part or all of the L1P RAM as normal RAM or as cache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.

The L1P is divided into two regions—denoted L1P region 0 and L1P region 1. This is the L1P architecture on the DM643x DMP:

∙L1P region 0: Not populated with memory.

∙L1P region 1: Populated with memory that can be configured as mapped memory or cache. The L1P region 1 memory has 0 wait state. This region is shown as “L1P RAM/Cache” in the device-specific data manual.

The DM643x DMP does not support the L1P memory protection feature of the standard C64x+ Megamodule.

Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862) and to the L1P controller section of the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the L1P controller and for a description of its control registers.

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TMS320C64x+ Megamodule

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Notational Conventions Read This FirstAbout This Manual Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaPower-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewExternal Memory Memory MapDSP Internal Memory L1P, L1D, L2 Internal PeripheralsExternal Memory Interface Memory Interfaces Overview1 DDR2 External Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsCore Domains OverviewClock Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Voltage Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlSystem PLLC1 Output Clocks Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPllout PLL2 ControlDDR PLLC2 Output Clocks Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Base Address End Address Size PLL and Reset Controller ListPLL and Reset Controller Registers PLL Controller RegistersPeripheral ID Register PID Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 D1END2EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden Goset PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat StableALN3 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN2Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 Obsen Auxen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions ObsenBpon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Obson AuxonSYS3ON SYS2ON SYS1ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module StatesExecuting State Transitions Local ResetPower Domain State Transitions Module State TransitionsPSC Interrupts IcePick Emulation CommandsIcePick Emulation Support in the PSC Interrupt EventsLocal Reset Emulation Events Interrupt RegistersModule State Emulation Events PSC Registers Power and Sleep Controller PSC RegistersInterrupt Handling Offset Register DescriptionPeripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 State Power Domain Status 0 Register PDSTAT0Pordone POR PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsEmuihbie Emurstie Lrst Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewModule Clock ON/OFF PLL Bypass and Power DownClock Management Module Clock Frequency ScalingDSP Module Clock ON/OFF DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock on3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Identification Device ConfigurationDevice Boot Configuration Status Pin Multiplexing Control3 DDR2 VTP Control Timer ControlVpss Clock and DAC Control HPI ControlTMS320DM643x DMP Master IDs Bandwidth ManagementBus Master DMA Priority Control DSP CFGTMS320DM643x DMP Default Master Priorities Edma Transfer Controller ConfigurationBoot Control DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.2 Reset10.1 10.3Reset Types Reset PinsDevice Configurations at Reset Type Initiator EffectDSP Module Reset DSP ResetDSP Local Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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