Texas Instruments TMS320DM643x 3.3 V I/O Power Down, Video DAC Power Down, DSP Module Clock Off

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3.3 V I/O Power Down

7.4.2.2DSP Module Clock Off

In the clock Disable state, the DSP’s module clock is disabled, while DSP reset remains de-asserted. This state is typically used to disable the DSP clock to save power. As mentioned in Section 7.4.2, the DSP cannot put itself in Disable state. An external host is responsible for performing this task. For example, it can be an external host interfacing through the HPI or PCI peripheral.

∙Host: Notify the DSP to prepare for power-down.

∙DSP: Drain all existing operations and ensure there are no accesses to the C64x+ megamodule prior to DSP power-down.

–Program the PSC to disable all master peripherals (except the Host) that are capable of initiating transfers to the C64x+ Megamodule.

–Check EDMA transfer status to ensure there is no outstanding EDMA transfers that can access the C64x+ Megamodule.

∙DSP: Prepare for power-down.

–Set PDCCMD to 0001 5555h. PDCCMD is a control register in the DSP power-down controller module.

Note: This register can only be written while the DSP is in supervisor mode.

–Enable one of the interrupts that the host would like to use to wake the DSP in the DSP clock-on sequence.

–Execute the IDLE instruction. IDLE is a program instruction in the C64x+ CPU instruction set. When the CPU executes IDLE, the PDC is notified and initiates DSP power-down according to the bits that you set in the PDCCMD (0181 0000h) register. See the TMS320C64x+ DSP Megamodule Reference Guide (SPRU871) for more information on the PDC and the IDLE instruction.

∙Host: Disable the DSP clock.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. You must wait for the power domain to finish any previously initiated transitions before initiating a new transition.

–Set the NEXT bit in MDCTL39 to 2h to prepare the DSP module for a disable transition.

–Set the GO[0] bit in PTCMD to 1 to initiate the state transition.

–Wait for the GOSTAT[0] bit in PTSTAT to clear to 0. The domain is only safely in the new state after the GOSTAT[0] bit is cleared to 0.

–Wait for the STATE bit in MDSTAT39 to change to 2h. The module is only safely in the new state after the STATE bit in MDSTAT39 changes to reflect the new state.

7.53.3 V I/O Power Down

The 3.3 V I/O drivers are fabricated out of 1.8 V transistors with design techniques that require a DC bias current. These I/O cells have a power-down mode that turns off the DC current. The VDD3P3V_PWDN register of the System Module controls this standby mode. Refer to the device-specific data manual for more details on the VDD3P3V_PWDN register.

7.6Video DAC Power Down

The DM643x DMP video processing back end (VPBE) includes four video digital-to-analog converters (DACs) to drive analog television displays. The Video Encoder (VENC) module of the VPBE includes registers for enabling/disabling the DACs. You can use the VIE bit in VMOD to force the analog output of the 4 DACs to a low level, regardless of the video signal. Furthermore, you can use the DAPD[3:0] bits in DACTST to disable each DAC independently. See the TMS320DM643x DMP Video Processing Back End (VPBE) User's Guide (SPRU952) for register descriptions and more detailed information on DAC power-down.

SPRU978E–March 2008

Power Management

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback About This Manual Read This FirstNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCPower-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryDSP Internal Memory L1P, L1D, L2 Memory MapExternal Memory Internal Peripherals1 DDR2 External Memory Interface Memory Interfaces OverviewExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingClock Domains OverviewCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsHecc Overall Clocking DiagramExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core Frequency FlexibilityCore Voltage DividerExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModuleSteps for Changing PLL1/Core Domain Frequency Device Clock GenerationSystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersDDR PLLC2 Output Clocks PLL2 ControlPllout Output Clock Used bySteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Registers PLL and Reset Controller ListPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Field Descriptions Reset Type Status Register RstypePeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register PllmPLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 3 Register PLLDIV3 PLL Controller Divider 2 Register PLLDIV2D2EN D3ENOD1EN Oscillator Divider 1 Register OSCDIV1Bypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden PLL Controller Status Register Pllstat PLL Controller Command Register PllcmdGoset StableALN2 ALN1 PLL Controller Clock Align Control Register AlnctlALN3 ALN2Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 18. Clock Enable Control Register Cken Field Descriptions Clock Enable Control Register CkenObsen Auxen Obsen19. Clock Status Register Ckstat Field Descriptions Clock Status Register CkstatBpon Obson Auxon20. Sysclk Status Register Systat Field Descriptions Sysclk Status Register SystatSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Power Domain States Power Domain and Module StatesModule States Module StatesPower Domain State Transitions Local ResetExecuting State Transitions Module State TransitionsIcePick Emulation Support in the PSC IcePick Emulation CommandsPSC Interrupts Interrupt EventsLocal Reset Emulation Events Interrupt RegistersModule State Emulation Events Interrupt Handling Power and Sleep Controller PSC RegistersPSC Registers Offset Register DescriptionPeripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 Pordone POR Power Domain Status 0 Register PDSTAT0State PordoneNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATn15. Module Control n Register MDCTLn Field Descriptions Module Control n Register MDCTLnEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionClock Management PLL Bypass and Power DownModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Modes DSP Sleep Mode ManagementDSP Module Clock ON/OFF DSP Module Clock on3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Boot Configuration Status Device ConfigurationDevice Identification Pin Multiplexing ControlVpss Clock and DAC Control Timer Control3 DDR2 VTP Control HPI ControlBus Master DMA Priority Control Bandwidth ManagementTMS320DM643x DMP Master IDs DSP CFGBoot Control Edma Transfer Controller ConfigurationTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.1 Reset10.2 10.3Device Configurations at Reset Reset PinsReset Types Type Initiator EffectDSP Local Reset DSP ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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