Texas Instruments TMS320DM643x manual Power Domain and Module States, Power Domain States

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Power Domain and Module States

6.3Power Domain and Module States

Note: The effects of DSP local reset and DSP module reset have not been fully validated; therefore, these resets are not supported and should not be used. Instead, the POR or RESET pins should be used to reset the entire DSP.

Table 6-1shows the state of each module after chip Power-on Reset (POR), Warm Reset (RESET), or Max Reset. These states are defined in the following sections.

6.3.1 Power Domain States

A power domain can only be in one of two states: ON or OFF, defined as follows:

∙ON: power to the power domain is on.

∙OFF: power to the power domain is off.

In the DM643x DMP, the AlwaysOn Power Domain is always in the ON state when the chip is powered-on.

6.3.2 Module States

A module can be in one of four states: Disable, Enable, SyncReset, or SwRstDisable. These four states correspond to combinations of module reset asserted or de-asserted and module clock on or off, as shown in Table 6-2.

Table 6-2. Module States

Module State

Module Reset

Module Clock

Module State Definition

Enable

De-asserted

On

A module in the enable state has its module reset de-asserted and

 

 

 

it has its clock on. This is the normal run-time state for a given

 

 

 

module.

Disable

De-asserted

Off

A module in the disable state has its module reset de-asserted and

 

 

 

it has its clock off. This state is typically used for disabling a module

 

 

 

clock to save power. The DM643x DMP is designed in full static

 

 

 

CMOS, so when you stop a module clock, it retains the module's

 

 

 

state. When the clock is restarted, the module resumes operating

 

 

 

from the stopping point.

SyncReset

Asserted

On

A module in the SyncReset state has its module reset asserted and

 

 

 

it has its clock on. Generally, software is not expected to initiate this

 

 

 

state.

SwRstDisable

Asserted

Off

A module in the SwResetDisable state has its module reset

 

 

 

asserted and it has its clock set to off. After initial power-on, most

 

 

 

modules are in the SyncRst state by default (see Table 6-1).

 

 

 

Generally, software is not expected to initiate this state.

Note: Module Reset is defined to completely reset a given module, so that all hardware returns to its default state. See Chapter 10 for more information on module reset.

For more information on power management, see Chapter 7.

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Power and Sleep Controller

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Read This First About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Introduction Block DiagramPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaInternal Peripherals Power-Down Controller PDCInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewMemory Map DSP Internal Memory L1P, L1D, L2External Memory Internal PeripheralsMemory Interfaces Overview 1 DDR2 External Memory InterfaceExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsOverview Clock DomainsCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Frequency Flexibility Example PLL1 Frequencies and Dividers 27 MHZ Clock InputCore Voltage Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlDevice Clock Generation Steps for Changing PLL1/Core Domain FrequencySystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPLL2 Control DDR PLLC2 Output ClocksPllout Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller List PLL and Reset Controller RegistersPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Reset Type Status Register Rstype Field DescriptionsPeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm PLL Controller Divider 1 Register PLLDIV1PLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 2 Register PLLDIV2 PLL Controller Divider 3 Register PLLDIV3D2EN D3ENOscillator Divider 1 Register OSCDIV1 OD1EN13. Bypass Divider Register Bpdiv Field Descriptions Bypass Divider Register BpdivBpden PLL Controller Command Register Pllcmd PLL Controller Status Register PllstatGoset StablePLL Controller Clock Align Control Register Alnctl ALN2 ALN1ALN3 ALN2SYS3 SYS2 SYS1 Plldiv Ratio Change Status Register DchangeSYS3 Clock Enable Control Register Cken 18. Clock Enable Control Register Cken Field DescriptionsObsen Auxen ObsenClock Status Register Ckstat 19. Clock Status Register Ckstat Field DescriptionsBpon Obson AuxonSysclk Status Register Systat 20. Sysclk Status Register Systat Field DescriptionsSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration DM643x DMP Default Module Configuration Power Domain and Module TopologyNumber Module Name Default Module State MDSTAT.STATE Power Domain and Module States Power Domain StatesModule States Module StatesLocal Reset Power Domain State TransitionsExecuting State Transitions Module State TransitionsIcePick Emulation Commands IcePick Emulation Support in the PSCPSC Interrupts Interrupt EventsInterrupt Registers Local Reset Emulation EventsModule State Emulation Events Power and Sleep Controller PSC Registers Interrupt HandlingPSC Registers Offset Register DescriptionInterrupt Evaluation Register Inteval Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Module Error Clear Register 1 MERRCR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Status Register Ptstat Power Domain Transition Command Register PtcmdGOSTAT0 Power Domain Status 0 Register PDSTAT0 Pordone PORState PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsModule Control n Register MDCTLn 15. Module Control n Register MDCTLn Field DescriptionsEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewPLL Bypass and Power Down Clock ManagementModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Mode Management DSP Sleep ModesDSP Module Clock ON/OFF DSP Module Clock onVideo DAC Power Down 3.3 V I/O Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Configuration Device Boot Configuration StatusDevice Identification Pin Multiplexing ControlTimer Control Vpss Clock and DAC Control3 DDR2 VTP Control HPI ControlBandwidth Management Bus Master DMA Priority ControlTMS320DM643x DMP Master IDs DSP CFGEdma Transfer Controller Configuration Boot ControlTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback Reset 10.110.2 10.3Reset Pins Device Configurations at ResetReset Types Type Initiator EffectDSP Reset DSP Local ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Table A-1. Document Revision History Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid
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