Texas Instruments TMS320DM643x manual Clock Status Register Ckstat, Bpon, Obson Auxon

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PLL Controller Registers

5.4.15 Clock Status Register (CKSTAT)

The clock status register (CKSTAT) is shown in Figure 5-17and described in Table 5-19. CKSTAT shows clock status for all clocks, except SYSCLKn.

Figure 5-17. Clock Status Register (CKSTAT)

31					16
	Reserved
	R-0
15	4	3	2	1	0
Reserved		BPON	Rsvd	OBSON	AUXON
R-0		R-1	R-0	R-0 or 1(1)	R-0 or 1(2)

LEGEND: R = Read only; -n= value after reset

(1)For PLLC1, OBSON defaults to 1; for PLLC2, OBSON is reserved and defaults to 0.

(2)For PLLC1, AUXON defaults to 1; for PLLC2, AUXON is reserved and defaults to 0.

Table 5-19. Clock Status Register (CKSTAT) Field Descriptions

Bit	Field	Value	Description
31-4	Reserved	0	Reserved
3	BPON		SYSCLKBP on status. SYSCLKBP is controlled in the bypass divider register (BPDIV).
		0	SYSCLKBP is off.
		1	SYSCLKBP is on.
2	Reserved	0	Reserved
1	OBSON		OBSCLK on status. OBSCLK is controlled in the oscillator divider 1 register (OSCDIV1) and by the
			OBSEN bit in the clock enable control register (CKEN). Not applicable on PLLC2 (this bit is reserved).
		0	OBSCLK is off.
		1	OBSCLK is on.
0	AUXON		AUXCLK on status. AUXCLK is controlled by the AUXEN bit in the clock enable control register
			(CKEN). Not applicable on PLLC2 (this bit is reserved).
		0	AUXCLK is off.
		1	AUXCLK is on.

SPRU978E–March 2008	PLL Controller	59
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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Read This FirstAbout This Manual Notational ConventionsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCInterrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryInternal Peripherals Memory MapDSP Internal Memory L1P, L1D, L2 External MemoryAsynchronous Emif Interface Memory Interfaces Overview1 DDR2 External Memory Interface External Memory InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingSystem Clock Modes and Fixed Ratios for Core Clock Domains OverviewClock Domains Core DomainsHecc Overall Clocking DiagramDivider Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core VoltageExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModulePLLC1 Output Clock Used by Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency System PLLC1 Output ClocksInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersOutput Clock Used by PLL2 ControlDDR PLLC2 Output Clocks PlloutSteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL Controller Registers PLL and Reset Controller ListPLL and Reset Controller Registers PLL and Reset Controller Base Address End Address SizePeripheral ID Register PID Field Descriptions Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PIDPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlD1EN PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register Pllm Field DescriptionsD3EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D2ENOD1EN Oscillator Divider 1 Register OSCDIV1Bpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions Stable PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat GosetALN2 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN3SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 Obsen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions Obsen AuxenObson Auxon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions BponSYS3ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ON SYS2ON SYS1ONPower and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Module States Power Domain and Module StatesPower Domain States Module StatesModule State Transitions Local ResetPower Domain State Transitions Executing State TransitionsInterrupt Events IcePick Emulation CommandsIcePick Emulation Support in the PSC PSC InterruptsModule State Emulation Events Local Reset Emulation EventsInterrupt Registers Offset Register Description Power and Sleep Controller PSC RegistersInterrupt Handling PSC RegistersInterrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Clear Register 1 MERRCR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1 Field DescriptionsGOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat Pordone Power Domain Status 0 Register PDSTAT0Pordone POR StateNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATnEmuihbie Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions Emuihbie Emurstie LrstSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionModule Clock Frequency Scaling PLL Bypass and Power DownClock Management Module Clock ON/OFFDSP Module Clock on DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock ON/OFFDSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Pin Multiplexing Control Device ConfigurationDevice Boot Configuration Status Device IdentificationHPI Control Timer ControlVpss Clock and DAC Control 3 DDR2 VTP ControlDSP CFG Bandwidth ManagementBus Master DMA Priority Control TMS320DM643x DMP Master IDsDSP DMA DSP CFG Emac Edma Transfer Controller ConfigurationBoot Control TMS320DM643x DMP Default Master PrioritiesSubmit Documentation Feedback 10.3 Reset10.1 10.2Type Initiator Effect Reset PinsDevice Configurations at Reset Reset TypesSoftware Reset Disable SwRstDisable DSP ResetDSP Local Reset DSP Module ResetSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP