Texas Instruments TMS320DM643x manual Changing PLL Multiplier

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PLL2 Control

5.3.2.3Changing PLL Multiplier

If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0) and the PLL stabilization time is previously met (step 7 in Section 5.3.2.2), follow this procedure to change PLL2 multiplier.

1.Before changing the PLL frequency, switch to PLL bypass mode:

a.Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect.

b.Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode).

c.Wait for 4 MXI cycles to ensure PLLC switches to bypass mode properly.

2.Clear the PLLRST bit in PLLCTL to 0 (reset PLL).

3.Clear the PLLDIS bit in PLLCTL to 0 (enable the PLL) to allow PLL outputs to start toggling. Note that the PLLC is still at PLL bypass mode; therefore, the toggling PLL output does not get propagated to the rest of the device.

4.Program the required multiplier value in PLLM.

5.If necessary, program PLLDIV1 and PLLDIV2 registers to change the SYSCLK1 and SYSCLK2 divide values:

a.Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress.

b.Program the RATIO field in PLLDIV1 and PLLDIV2 with the desired divide factors. For PLLC2, there is no specific frequency ratio requirements between SYSCLK1 and SYSCLK2. Make sure in this step you leave the PLLDIV1.D1EN and PLLDIV2.D2EN bits set (default).

c.Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition. During this transition, SYSCLK1 and SYSCLK2 are paused momentarily.

d.Wait for N number of PLLDIVn source clock cycles to ensure divider changes have completed. See Section 5.3.2.4 for the formula on calculating the number of cycles N.

e.Wait for the GOSTAT bit in PLLSTAT to clear to 0.

6.Wait for PLL to reset properly. See the device-specific data manual for PLL reset time.

7.Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset.

8.Wait for PLL to lock. See the device-specific data manual for PLL lock time.

9.Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode.

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PLL Controller

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Notational Conventions Read This FirstAbout This Manual Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Introduction Block DiagramPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaInternal Peripherals Power-Down Controller PDCInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewExternal Memory Memory MapDSP Internal Memory L1P, L1D, L2 Internal PeripheralsExternal Memory Interface Memory Interfaces Overview1 DDR2 External Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsCore Domains OverviewClock Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Voltage Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlSystem PLLC1 Output Clocks Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPllout PLL2 ControlDDR PLLC2 Output Clocks Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Base Address End Address Size PLL and Reset Controller ListPLL and Reset Controller Registers PLL Controller RegistersPeripheral ID Register PID Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 D1END2EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D3ENOscillator Divider 1 Register OSCDIV1 OD1EN13. Bypass Divider Register Bpdiv Field Descriptions Bypass Divider Register BpdivBpden Goset PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat StableALN3 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN2SYS3 SYS2 SYS1 Plldiv Ratio Change Status Register DchangeSYS3 Obsen Auxen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions ObsenBpon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Obson AuxonSYS3ON SYS2ON SYS1ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration DM643x DMP Default Module Configuration Power Domain and Module TopologyNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module StatesExecuting State Transitions Local ResetPower Domain State Transitions Module State TransitionsPSC Interrupts IcePick Emulation CommandsIcePick Emulation Support in the PSC Interrupt EventsInterrupt Registers Local Reset Emulation EventsModule State Emulation Events PSC Registers Power and Sleep Controller PSC RegistersInterrupt Handling Offset Register DescriptionInterrupt Evaluation Register Inteval Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Status Register Ptstat Power Domain Transition Command Register PtcmdGOSTAT0 State Power Domain Status 0 Register PDSTAT0Pordone POR PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsEmuihbie Emurstie Lrst Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewModule Clock ON/OFF PLL Bypass and Power DownClock Management Module Clock Frequency ScalingDSP Module Clock ON/OFF DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock onVideo DAC Power Down 3.3 V I/O Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Identification Device ConfigurationDevice Boot Configuration Status Pin Multiplexing Control3 DDR2 VTP Control Timer ControlVpss Clock and DAC Control HPI ControlTMS320DM643x DMP Master IDs Bandwidth ManagementBus Master DMA Priority Control DSP CFGTMS320DM643x DMP Default Master Priorities Edma Transfer Controller ConfigurationBoot Control DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.2 Reset10.1 10.3Reset Types Reset PinsDevice Configurations at Reset Type Initiator EffectDSP Module Reset DSP ResetDSP Local Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Table A-1. Document Revision History Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid