Texas Instruments TMS320DM643x manual 3 DDR2/EMIF Clock, Example PLL2 Frequencies Core Voltage =

Page 33

www.ti.com

Clock Domains

4.2.3 DDR2/EMIF Clock

The DDR2 interface has a dedicated clock driven from PLL2. This is a separate clock system from the PLL1 clocks provided to other components of the system. This dedicated clock allows the reduction of the core clock rates to save power while maintaining the required minimum clock rate (125 MHZ) for DDR2. PLL2 must be configured to output a 2× clock to the DDR2 PHY interface.

The DM643x DMP video DACs are capable of driving high quality progressive television displays, if driven by a 54 MHZ input clock sourced by PLL2 (see the TMS320DM643x DMP Video Processing Back End (VPBE) User's Guide (SPRU952) for more detailed information). This will limit the possible PLL2 settings to a multiple of 54 MHZ so that the VPBE clock can be derived with a simple integer clock divider.

All of the following frequency ranges and multiplier/divider ratios in the device-specific data manual must be adhered to when configuring PLL2:

∙Input clock frequency range (MXI/CLKIN)

∙PLL2 multiplier (PLLM) range

∙PLL2 output (PLLOUT) frequency range based on core voltage (1.05V or 1.2V) of the device

Table 4-3and Table 4-4show some PLL2/DDR2 clock rates assuming a MXI/CLKIN frequency of 27 MHZ. These tables also indicate settings that are multiples of 54 MHZ.

Table 4-3. Example PLL2 Frequencies (Core Voltage = 1.2V)

 

PLL2 PLLOUT Freq

SYSCLK1

PHY [2× clock]

 

 

PLL2 Multiplier

(MHZ)

Divider(1)

(MHZ)

DDR2 Clock (MHZ)

54 MHZ Multiple

28

756.0

3

252.0

126.0

Yes

19

513.0

2

256.5

128.3

No

29

783.0

3

261.0

130.5

No

20

540.0

2

270.0

135.0

Yes

31

837.0

3

279.0

139.5

No

21

567.0

2

283.5

141.8

No

32

864.0

3

288.0

144.0

Yes

22

594.0

2

297.0

148.5

Yes

23

621.0

2

310.5

155.3

No

24

648.0

2

324.0

162.0

Yes

25

675.0

2

337.5

168.8

No

(1)The RATIO bit in PLLDIVn is programmed as Divider - 1. For example, for SYSCLK1 divider of 3, you should program PLLDIV1.RATIO = 2.

Table 4-4. Example PLL2 Frequencies (Core Voltage = 1.05V)

 

PLL2 PLLOUT Freq

SYSCLK1

PHY [2× clock]

 

 

PLL2 Multiplier

(MHZ)

Divider(1)

(MHZ)

DDR2 Clock (MHZ)

54 MHZ Multiple

19

513.0

2

256.5

128.3

No

20

540.0

2

270.0

135.0

Yes

21

567.0

2

283.5

141.8

No

22

594.0

2

297.0

148.5

Yes

23

621.0

2

310.5

155.3

No

24

648.0

2

324.0

162.0

Yes

(1)The RATIO bit in PLLDIVn is programmed as Divider - 1. For example, for SYSCLK1 divider of 3, you should program PLLDIV1.RATIO = 2.

SPRU978E–March 2008

Device Clocking

33

Page 32 Page 34
Image 33
Page 32 Page 34
Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback About This Manual Read This FirstNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCPower-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryDSP Internal Memory L1P, L1D, L2 Memory MapExternal Memory Internal Peripherals1 DDR2 External Memory Interface Memory Interfaces OverviewExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingClock Domains OverviewCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsHecc Overall Clocking DiagramExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core Frequency FlexibilityCore Voltage DividerExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModuleSteps for Changing PLL1/Core Domain Frequency Device Clock GenerationSystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersDDR PLLC2 Output Clocks PLL2 ControlPllout Output Clock Used bySteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Registers PLL and Reset Controller ListPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Field Descriptions Reset Type Status Register RstypePeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register PllmPLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 3 Register PLLDIV3 PLL Controller Divider 2 Register PLLDIV2D2EN D3ENOD1EN Oscillator Divider 1 Register OSCDIV1Bypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden PLL Controller Status Register Pllstat PLL Controller Command Register PllcmdGoset StableALN2 ALN1 PLL Controller Clock Align Control Register AlnctlALN3 ALN2Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 18. Clock Enable Control Register Cken Field Descriptions Clock Enable Control Register CkenObsen Auxen Obsen19. Clock Status Register Ckstat Field Descriptions Clock Status Register CkstatBpon Obson Auxon20. Sysclk Status Register Systat Field Descriptions Sysclk Status Register SystatSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Power Domain States Power Domain and Module StatesModule States Module StatesPower Domain State Transitions Local ResetExecuting State Transitions Module State TransitionsIcePick Emulation Support in the PSC IcePick Emulation CommandsPSC Interrupts Interrupt EventsLocal Reset Emulation Events Interrupt RegistersModule State Emulation Events Interrupt Handling Power and Sleep Controller PSC RegistersPSC Registers Offset Register DescriptionPeripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 Pordone POR Power Domain Status 0 Register PDSTAT0State PordoneNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATn15. Module Control n Register MDCTLn Field Descriptions Module Control n Register MDCTLnEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionClock Management PLL Bypass and Power DownModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Modes DSP Sleep Mode ManagementDSP Module Clock ON/OFF DSP Module Clock on3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Boot Configuration Status Device ConfigurationDevice Identification Pin Multiplexing ControlVpss Clock and DAC Control Timer Control3 DDR2 VTP Control HPI ControlBus Master DMA Priority Control Bandwidth ManagementTMS320DM643x DMP Master IDs DSP CFGBoot Control Edma Transfer Controller ConfigurationTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.1 Reset10.2 10.3Device Configurations at Reset Reset PinsReset Types Type Initiator EffectDSP Local Reset DSP ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
Top Page Image Contents