Texas Instruments TMS320DM643x manual Power Domain Control 0 Register PDCTL0, Next

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PSC Registers

6.7.8 Power Domain Control 0 Register (PDCTL0)

The power domain control n register (PDCTL0) is shown in Figure 6-9and described in Table 6-13. PDCTL0 applies to the AlwaysOn power domain.

Figure 6-9. Power Domain Control 0 Register (PDCTL0)

31		16
Reserved
R-0
15	1	0
Reserved		NEXT
R-0		R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 6-13. Power Domain Control 0 Register (PDCTL0) Field Descriptions

Bit	Field	Value	Description
31-1	Reserved	0	Reserved
0	NEXT		Power domain next state.
		0	Power domain off.
		1	Power domain on. AlwaysOn domain must always be programmed to this value.

SPRU978E–March 2008	Power and Sleep Controller	73
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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback About This Manual Read This FirstNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Introduction Block DiagramPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCInternal Peripherals Power-Down Controller PDCInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryDSP Internal Memory L1P, L1D, L2 Memory MapExternal Memory Internal Peripherals1 DDR2 External Memory Interface Memory Interfaces OverviewExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingClock Domains OverviewCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsHecc Overall Clocking DiagramExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core Frequency FlexibilityCore Voltage DividerExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModuleSteps for Changing PLL1/Core Domain Frequency Device Clock GenerationSystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersDDR PLLC2 Output Clocks PLL2 ControlPllout Output Clock Used bySteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Registers PLL and Reset Controller ListPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Field Descriptions Reset Type Status Register RstypePeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register PllmPLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 3 Register PLLDIV3 PLL Controller Divider 2 Register PLLDIV2D2EN D3ENOD1EN Oscillator Divider 1 Register OSCDIV113. Bypass Divider Register Bpdiv Field Descriptions Bypass Divider Register BpdivBpden PLL Controller Status Register Pllstat PLL Controller Command Register PllcmdGoset StableALN2 ALN1 PLL Controller Clock Align Control Register AlnctlALN3 ALN2SYS3 SYS2 SYS1 Plldiv Ratio Change Status Register DchangeSYS3 18. Clock Enable Control Register Cken Field Descriptions Clock Enable Control Register CkenObsen Auxen Obsen19. Clock Status Register Ckstat Field Descriptions Clock Status Register CkstatBpon Obson Auxon20. Sysclk Status Register Systat Field Descriptions Sysclk Status Register SystatSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration DM643x DMP Default Module Configuration Power Domain and Module TopologyNumber Module Name Default Module State MDSTAT.STATE Power Domain States Power Domain and Module StatesModule States Module StatesPower Domain State Transitions Local ResetExecuting State Transitions Module State TransitionsIcePick Emulation Support in the PSC IcePick Emulation CommandsPSC Interrupts Interrupt EventsInterrupt Registers Local Reset Emulation EventsModule State Emulation Events Interrupt Handling Power and Sleep Controller PSC RegistersPSC Registers Offset Register DescriptionInterrupt Evaluation Register Inteval Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Status Register Ptstat Power Domain Transition Command Register PtcmdGOSTAT0 Pordone POR Power Domain Status 0 Register PDSTAT0State PordoneNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATn15. Module Control n Register MDCTLn Field Descriptions Module Control n Register MDCTLnEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionClock Management PLL Bypass and Power DownModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Modes DSP Sleep Mode ManagementDSP Module Clock ON/OFF DSP Module Clock onVideo DAC Power Down 3.3 V I/O Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Boot Configuration Status Device ConfigurationDevice Identification Pin Multiplexing ControlVpss Clock and DAC Control Timer Control3 DDR2 VTP Control HPI ControlBus Master DMA Priority Control Bandwidth ManagementTMS320DM643x DMP Master IDs DSP CFGBoot Control Edma Transfer Controller ConfigurationTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.1 Reset10.2 10.3Device Configurations at Reset Reset PinsReset Types Type Initiator EffectDSP Local Reset DSP ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Table A-1. Document Revision History Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid