Texas Instruments TMS320DM643x manual Video Processing Back End

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Clock Domains

4.2.5 Video Processing Back End

The video processing back end (VPBE) is a submodule of the video processing subsystem (VPSS). The VPBE must interface with a variety of LCDs, as well as the 4-channel DAC module. There are many different types of LCDs, which require many different specific frequencies. The range of frequencies that the pin interface needs to run is 6.25 MHZ to 75 MHZ.

There are two asynchronous clock domains in the VPBE: the external clock domain (6.25 MHZ to 75 MHZ) and the internal (system) clock domain, which is at the DSP ÷ 3 clock rate.

The external clock domain can get its clock from 4 sources:

∙PLLC1 SYSCLKBP (typically 27 MHZ, MXI/CLKIN divide by 1)

∙The VPBECLK input pin

∙The VPFE pixel clock input (PCLK)

∙PLLC2 SYSCLK2 (a divide down from PLL2)

The 4 DACs are hooked up to the VENC module that is in the VPBE. The data flow between the VPBE and DACs is synchronous. The various possible clocking modes are shown in Figure 4-2and described in Table 4-6.

The DACs can have their clocks independently gated off when the DACs are not being used. This is described in Chapter 7.

Figure 4-2. VPBE/DAC Clocking

 

 

 

 

VPSS

venc_sclk_osd

 

 

VPSS_CLKCTL.MUXSEL

 

 

 

 

 

 

venc_sclk_enc

 

 

 

 

CG

OSD

PCLK

3

 

1

 

 

 

VENC

VPBECLK

2

CLK_VENC

 

0

 

 

0

 

 

 

 

 

 

 

1

 

venc_div2

 

 

 

 

 

SYSCLKBP

 

 

 

 

 

2

CLK_DAC

 

 

 

0

 

DACs

 

 

 

PLLDIV2

CLK54

 

 

 

1

 

 

 

 

PLLC1

 

VPSS_CLKCTL.MUXSEL

CLK54 CLK_VENC CLK_DAC

 

 

 

 

 

 

0

Off

27 MHz

27 MHz

MXI

PLL2

 

1h

54

54 MHz

54 MHz

 

2h

Off

VPBECLK

VPBECLK

 

 

 

 

PLLDIV1

DDR_CLKx2

3h

Off

PCLK

Off

SPRU978E–March 2008

Device Clocking

35

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Read This FirstAbout This Manual Notational ConventionsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCInterrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryInternal Peripherals Memory MapDSP Internal Memory L1P, L1D, L2 External MemoryAsynchronous Emif Interface Memory Interfaces Overview1 DDR2 External Memory Interface External Memory InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingSystem Clock Modes and Fixed Ratios for Core Clock Domains OverviewClock Domains Core DomainsHecc Overall Clocking Diagram Divider Core Frequency Flexibility Example PLL1 Frequencies and Dividers 27 MHZ Clock Input Core VoltageExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModulePLLC1 Output Clock Used by Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency System PLLC1 Output ClocksInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersOutput Clock Used by PLL2 ControlDDR PLLC2 Output Clocks PlloutSteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL Controller Registers PLL and Reset Controller ListPLL and Reset Controller Registers PLL and Reset Controller Base Address End Address SizePeripheral ID Register PID Field Descriptions Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PIDPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlD1EN PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register Pllm Field DescriptionsD3EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D2ENOD1EN Oscillator Divider 1 Register OSCDIV1Bpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions Stable PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat GosetALN2 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN3SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 Obsen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions Obsen AuxenObson Auxon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions BponSYS3ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ON SYS2ON SYS1ONPower and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Module States Power Domain and Module StatesPower Domain States Module StatesModule State Transitions Local ResetPower Domain State Transitions Executing State TransitionsInterrupt Events IcePick Emulation CommandsIcePick Emulation Support in the PSC PSC InterruptsModule State Emulation Events Local Reset Emulation EventsInterrupt Registers Offset Register Description Power and Sleep Controller PSC RegistersInterrupt Handling PSC RegistersInterrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Clear Register 1 MERRCR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1 Field DescriptionsGOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat Pordone Power Domain Status 0 Register PDSTAT0Pordone POR StateNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATnEmuihbie Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions Emuihbie Emurstie LrstSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionModule Clock Frequency Scaling PLL Bypass and Power DownClock Management Module Clock ON/OFFDSP Module Clock on DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock ON/OFFDSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Pin Multiplexing Control Device ConfigurationDevice Boot Configuration Status Device IdentificationHPI Control Timer ControlVpss Clock and DAC Control 3 DDR2 VTP ControlDSP CFG Bandwidth ManagementBus Master DMA Priority Control TMS320DM643x DMP Master IDsDSP DMA DSP CFG Emac Edma Transfer Controller ConfigurationBoot Control TMS320DM643x DMP Default Master PrioritiesSubmit Documentation Feedback 10.3 Reset10.1 10.2Type Initiator Effect Reset PinsDevice Configurations at Reset Reset TypesSoftware Reset Disable SwRstDisable DSP ResetDSP Local Reset DSP Module ResetSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP
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