Texas Instruments TMS320DM643x manual Interrupt Registers, Module State Emulation Events

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PSC Interrupts

The DM643x DMP is a single-processor device. The C64x+ CPU must not program its own module state. The C64x+ CPU module state can only be programmed by an external host (for example, PCI, HPI). As a result, interrupt events listed in Table 6-4can only occur in the scenario where an external host programs the C64x+ CPU module state but the emulator alters that desired state.

6.6.1.1Module State Emulation Events

A module state emulation event occurs when emulation alters the state of a module. Status is reflected in the EMUIHB bit in MDSTATn. In particular, a module state emulation event occurs under the following conditions:

∙When inhibit sleep is asserted by emulation and software attempts to transition the module out of the enable state.

∙When force active is asserted by emulation and module is not already in the enable state.

6.6.1.2Local Reset Emulation Events

A local reset emulation event occurs when emulation alters the local reset of a module. Status is reflected in the EMURST bit in MDSTATn. In particular, a module local reset emulation event occurs under the following conditions:

∙When assert reset is asserted by emulation although software de-asserted the local reset.

∙When wait reset is asserted by emulation.

∙When block reset is asserted by emulation and software attempts to change the state of local reset.

6.6.2Interrupt Registers

The PSC interrupt enable bits are the EMUIHBIE bit in MDCTL39 and the EMURSTIE bit in MDCTL39.

Note: To interrupt the DSP, the power and sleep controller interrupt (PSCINT) must also be enabled in the DSP interrupt controller. See Section 2.4.1 for more information on the interrupt controller.

The PSC interrupt status bits are the M[39] bit in MERRPR1, the EMUIHB bit in MDSTAT39, and the EMURST bit in MDSTAT39. The status bit in MERRPR1 is read by software to determine which module has generated an emulation interrupt, and then software can read the corresponding status bits in MDSTAT39 to determine which event caused the interrupt.

The PSC interrupt clear bit is the M[39] bit in MERRCR1.

The PSC interrupt evaluation bit is the ALLEV bit in INTEVAL. When set, this bit forces the PSC interrupt logic to re-evaluate event status. If any events are still active (if any status bits are set) when the ALLEV bit in INTEVAL is set to 1, the PSCINT is re-asserted to the DSP interrupt controller. Set the ALLEV bit in INTEVAL before exiting your PSCINT interrupt service routine to ensure that you do not miss any PSC interrupts.

See Section 6.7 for complete descriptions of all PSC registers.

SPRU978E–March 2008

Power and Sleep Controller

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback Related Documentation From Texas Instruments Read This FirstAbout This Manual Notational ConventionsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Introduction Block DiagramPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCInternal Peripherals Power-Down Controller PDCInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryInternal Peripherals Memory MapDSP Internal Memory L1P, L1D, L2 External MemoryAsynchronous Emif Interface Memory Interfaces Overview1 DDR2 External Memory Interface External Memory InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingSystem Clock Modes and Fixed Ratios for Core Clock Domains OverviewClock Domains Core DomainsHecc Overall Clocking DiagramDivider Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core VoltageExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModulePLLC1 Output Clock Used by Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency System PLLC1 Output ClocksInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersOutput Clock Used by PLL2 ControlDDR PLLC2 Output Clocks PlloutSteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL Controller Registers PLL and Reset Controller ListPLL and Reset Controller Registers PLL and Reset Controller Base Address End Address SizePeripheral ID Register PID Field Descriptions Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PIDPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlD1EN PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register Pllm Field DescriptionsD3EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D2ENOD1EN Oscillator Divider 1 Register OSCDIV113. Bypass Divider Register Bpdiv Field Descriptions Bypass Divider Register BpdivBpden Stable PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat GosetALN2 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN3SYS3 SYS2 SYS1 Plldiv Ratio Change Status Register DchangeSYS3 Obsen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions Obsen AuxenObson Auxon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions BponSYS3ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ON SYS2ON SYS1ONPower and Sleep Controller Power and Sleep Controller PSC Integration DM643x DMP Default Module Configuration Power Domain and Module TopologyNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module StatesModule State Transitions Local ResetPower Domain State Transitions Executing State TransitionsInterrupt Events IcePick Emulation CommandsIcePick Emulation Support in the PSC PSC InterruptsInterrupt Registers Local Reset Emulation EventsModule State Emulation Events Offset Register Description Power and Sleep Controller PSC RegistersInterrupt Handling PSC RegistersInterrupt Evaluation Register Inteval Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1 Field DescriptionsPower Domain Transition Status Register Ptstat Power Domain Transition Command Register PtcmdGOSTAT0 Pordone Power Domain Status 0 Register PDSTAT0Pordone POR StateNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATnEmuihbie Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions Emuihbie Emurstie LrstSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionModule Clock Frequency Scaling PLL Bypass and Power DownClock Management Module Clock ON/OFFDSP Module Clock on DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock ON/OFFVideo DAC Power Down 3.3 V I/O Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Pin Multiplexing Control Device ConfigurationDevice Boot Configuration Status Device IdentificationHPI Control Timer ControlVpss Clock and DAC Control 3 DDR2 VTP ControlDSP CFG Bandwidth ManagementBus Master DMA Priority Control TMS320DM643x DMP Master IDsDSP DMA DSP CFG Emac Edma Transfer Controller ConfigurationBoot Control TMS320DM643x DMP Default Master PrioritiesSubmit Documentation Feedback 10.3 Reset10.1 10.2Type Initiator Effect Reset PinsDevice Configurations at Reset Reset TypesSoftware Reset Disable SwRstDisable DSP ResetDSP Local Reset DSP Module ResetSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Table A-1. Document Revision History Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid
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