Texas Instruments TMS320DM643x manual Read This First, About This Manual, Notational Conventions

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Preface

SPRU978E–March 2008

Read This First

About This Manual

This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP).

Notational Conventions

This document uses the following conventions.

∙Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

∙Registers in this document are shown in figures and described in tables.

–Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

–Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DM643x DMP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRU983 — TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).

SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.

SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.

SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRU862 — TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C64x+ digital signal processor (DSP) of the TMS320C6000 DSP family can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C64x+ DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Boot Modes ResetList of Figures List of Tables Submit Documentation Feedback About This Manual Read This FirstNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals Components of the DSP Subsystem DSP Subsystem in TMS320DM643x DMPSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram 1 L1P Controller Memory ControllersL1D L1P3 L2 Controller 2 L1D ControllerInternal DMA Idma External Memory Controller EMCPower-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback Memory Map Memory Interfaces Overview System MemoryDSP Internal Memory L1P, L1D, L2 Memory MapExternal Memory Internal Peripherals1 DDR2 External Memory Interface Memory Interfaces OverviewExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Overview Clock Domains Device ClockingClock Domains OverviewCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsHecc Overall Clocking DiagramExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Core Frequency FlexibilityCore Voltage DividerExample PLL2 Frequencies Core Voltage = 3 DDR2/EMIF ClockPeripheral I/O Domain Clock 4 I/O DomainsVideo Processing Back End Possible Clocking Modes VPSSCLKCTL.MUXSEL Bit Clocking Mode DescriptionPLL Controller PLL1 Control PLL ModuleSteps for Changing PLL1/Core Domain Frequency Device Clock GenerationSystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-1. Calculating Number of Clock Cycles N Changing Sysclk DividersDDR PLLC2 Output Clocks PLL2 ControlPllout Output Clock Used bySteps for Changing PLL2 Frequency 2.1 DDR2 Considerations When Modifying PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Registers PLL and Reset Controller ListPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Field Descriptions Reset Type Status Register RstypePeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl Field Descriptions PLL Control Register PllctlPLL Controller Divider 1 Register PLLDIV1 PLL Multiplier Control Register PllmPLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 3 Register PLLDIV3 PLL Controller Divider 2 Register PLLDIV2D2EN D3ENOD1EN Oscillator Divider 1 Register OSCDIV1Bypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden PLL Controller Status Register Pllstat PLL Controller Command Register PllcmdGoset StableALN2 ALN1 PLL Controller Clock Align Control Register AlnctlALN3 ALN2Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 18. Clock Enable Control Register Cken Field Descriptions Clock Enable Control Register CkenObsen Auxen Obsen19. Clock Status Register Ckstat Field Descriptions Clock Status Register CkstatBpon Obson Auxon20. Sysclk Status Register Systat Field Descriptions Sysclk Status Register SystatSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Power Domain States Power Domain and Module StatesModule States Module StatesPower Domain State Transitions Local ResetExecuting State Transitions Module State TransitionsIcePick Emulation Support in the PSC IcePick Emulation CommandsPSC Interrupts Interrupt EventsLocal Reset Emulation Events Interrupt RegistersModule State Emulation Events Interrupt Handling Power and Sleep Controller PSC RegistersPSC Registers Offset Register DescriptionPeripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Clear Register 1 MERRCR1 Module Error Pending Register 1 MERRPR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 Pordone POR Power Domain Status 0 Register PDSTAT0State PordoneNext Power Domain Control 0 Register PDCTL014. Module Status n Register MDSTATn Field Descriptions Module Status n Register MDSTATn15. Module Control n Register MDCTLn Field Descriptions Module Control n Register MDCTLnEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management PSC and Pllc Overview Power Management Features DescriptionClock Management PLL Bypass and Power DownModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Modes DSP Sleep Mode ManagementDSP Module Clock ON/OFF DSP Module Clock on3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Boot Configuration Status Device ConfigurationDevice Identification Pin Multiplexing ControlVpss Clock and DAC Control Timer Control3 DDR2 VTP Control HPI ControlBus Master DMA Priority Control Bandwidth ManagementTMS320DM643x DMP Master IDs DSP CFGBoot Control Edma Transfer Controller ConfigurationTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.1 Reset10.2 10.3Device Configurations at Reset Reset PinsReset Types Type Initiator EffectDSP Local Reset DSP ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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