Texas Instruments TMS320DM643x Core Frequency Flexibility, Core Voltage, Divider, Multiplier

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Clock Domains

4.2.2 Core Frequency Flexibility

The core frequency domain clocks are supplied by the PLL controller 1 (PLLC1). These domain clocks are flexible, to a degree, within the limitations specified in the device-specific data manual. All of the following frequency ranges and multiplier/divider ratios in the data manual must be adhered to:

∙Input clock frequency range (MXI/CLKIN)

∙PLL1 multiplier (PLLM) range

∙PLL1 output (PLLOUT) frequency range based on the core voltage (1.05V or 1.2V) of the device

∙Maximum device speed

∙PLLC1's SYSCLK3:SYSCLK2:SYSCLK1 frequency ratio must be fixed to 1:3:6. For example, if SYSCLK1 is at 600 MHZ, SYSCLK2 must be at 200 MHZ, and SYSCLK3 must be at 100 MHZ.

As specified in the data manual, the PLLs can be driven by any input ranging from 20 to 30 MHZ. However, a 27 MHZ input is required if the video processing back end (VPBE) subsystem is needed to drive television displays with the integrated video DACs.

Table 4-2shows some example PLL1 multiplier and divider settings assuming MXI/CLKIN frequency of 27 MHZ. The Applicable to Device Core Voltage column indicates whether the setting is allowed for a given device core voltage. For example, the last row in Table 4-2(PLL1 multiplier 22 for a 27 MHZ clock input) only applies to devices with a core voltage 1.2V to meet the PLL1 output (PLLOUT) frequency range required in the data manual. In addition, you must ensure the SYSCLK1 frequency does not exceed the speed grade of the device. For example, for a device rated at 400 MHZ speed grade, SYSCLK1 must not exceed 400 MHZ.

Table 4-2. Example PLL1 Frequencies and Dividers (27 MHZ Clock Input)

 

 

CLKDIV1 Domain

CLKDIV3 Domain

CLKDIV6 Domain

Applicable to Device

 

 

(SYSCLK1)

(SYSCLK2)

(SYSCLK3)

Core Voltage

 

PLL1

 

 

 

 

 

 

 

 

PLL1

PLLOUT

Divider(1)

Freq

Divider(1)

Freq

Divider(1)

Freq

 

 

Multiplier

Freq (MHZ)

(MHZ)

(MHZ)

(MHZ)

1.2V

1.05V

15

405.0

1

405.0

3

135.0

6

67.5

Y

Y

16

432.0

1

432.0

3

144.0

6

72.0

Y

Y

17

459.0

1

459.0

3

153.0

6

76.5

Y

Y

18

486.0

1

486.0

3

162.0

6

81.0

Y

Y

19

513.0

1

513.0

3

171.0

6

85.5

Y

Y

20

540.0

1

540.0

3

180.0

6

90.0

Y

-

21

567.0

1

567.0

3

189.0

6

94.5

Y

-

22

594.0

1

594.0

3

198.0

6

99.0

Y

-

22

594.0

2

297.0

6

99.0

12

49.5

Y

-

(1)The RATIO bit in PLLDIVn is programmed as Divider - 1. For example, for a SYSCLK1 divider of 1, you should program PLLDIV1.RATIO = 0, PLLDIV2.RATIO = 2, PLLDIV3.RATIO = 5.

32

Device Clocking

SPRU978E–March 2008

 

 

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Read This First About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaInterrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewMemory Map DSP Internal Memory L1P, L1D, L2External Memory Internal PeripheralsMemory Interfaces Overview 1 DDR2 External Memory InterfaceExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsOverview Clock DomainsCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Frequency Flexibility Example PLL1 Frequencies and Dividers 27 MHZ Clock InputCore Voltage Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlDevice Clock Generation Steps for Changing PLL1/Core Domain FrequencySystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPLL2 Control DDR PLLC2 Output ClocksPllout Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller List PLL and Reset Controller RegistersPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Reset Type Status Register Rstype Field DescriptionsPeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm PLL Controller Divider 1 Register PLLDIV1PLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 2 Register PLLDIV2 PLL Controller Divider 3 Register PLLDIV3D2EN D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions PLL Controller Command Register Pllcmd PLL Controller Status Register PllstatGoset StablePLL Controller Clock Align Control Register Alnctl ALN2 ALN1ALN3 ALN2SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 Clock Enable Control Register Cken 18. Clock Enable Control Register Cken Field DescriptionsObsen Auxen ObsenClock Status Register Ckstat 19. Clock Status Register Ckstat Field DescriptionsBpon Obson AuxonSysclk Status Register Systat 20. Sysclk Status Register Systat Field DescriptionsSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Power Domain and Module States Power Domain StatesModule States Module StatesLocal Reset Power Domain State TransitionsExecuting State Transitions Module State TransitionsIcePick Emulation Commands IcePick Emulation Support in the PSCPSC Interrupts Interrupt EventsModule State Emulation Events Local Reset Emulation EventsInterrupt Registers Power and Sleep Controller PSC Registers Interrupt HandlingPSC Registers Offset Register DescriptionInterrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Pending Register 1 MERRPR1 Module Error Clear Register 1 MERRCR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsGOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat Power Domain Status 0 Register PDSTAT0 Pordone PORState PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsModule Control n Register MDCTLn 15. Module Control n Register MDCTLn Field DescriptionsEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewPLL Bypass and Power Down Clock ManagementModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Mode Management DSP Sleep ModesDSP Module Clock ON/OFF DSP Module Clock onDSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Configuration Device Boot Configuration StatusDevice Identification Pin Multiplexing ControlTimer Control Vpss Clock and DAC Control3 DDR2 VTP Control HPI ControlBandwidth Management Bus Master DMA Priority ControlTMS320DM643x DMP Master IDs DSP CFGEdma Transfer Controller Configuration Boot ControlTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback Reset 10.110.2 10.3Reset Pins Device Configurations at ResetReset Types Type Initiator EffectDSP Reset DSP Local ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP
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