Texas Instruments TMS320DM643x manual Device Identification, Device Configuration

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Overview

9.1Overview

The TMS320DM643x DMP System Module is a system-level module containing status and top-level control logic required by the device. The System Module consists of a set of status and control registers, accessible by the DSP, supporting all of the following system features and operations:

∙Device Identification

∙Device Configuration

–Pin multiplexing control

–Device boot configuration status

∙Power Management

–VDD 3.3 V I/O power-down control

∙Special Peripheral Status and Control

–Timer control

–VPSS clock and DAC control

–DDR2 VTP control

–HPI control

∙Bandwidth Management

–Bus master DMA priority control

–EDMA Transfer Channel configuration

∙Boot Control

This chapter describes the System Module.

9.2Device Identification

The DEVICE_ID register of the System Module contains a software readable version of the JTAG ID device. Software can use this register to determine the version of the device on which it is executing. The register format and description are shown in the device-specific data manual.

9.3Device Configuration

The System Module contains registers for controlling pin multiplexing and registers that reflect the boot configuration status.

9.3.1 Pin Multiplexing Control

The DM643x DMP makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. A combination of hardware configuration (configuration pins latched at device reset) and register program control (PINMUX0 and PINMUX1 registers) controls pin multiplexing to accomplish this. Hardware does not attempt to ensure that the proper pin multiplexing is selected for the peripherals or that interface mode is being used.

Detailed information about the pin multiplexing and control is covered in the device-specific data manual.

9.3.2 Device Boot Configuration Status

The device boot and configuration settings are latched at device reset (POR or RESET), and captured in the BOOTCFG register. See the device-specific data manual for details on this register and the boot and configuration settings.

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System Module

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Notational Conventions Read This FirstAbout This Manual Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaInterrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewExternal Memory Memory MapDSP Internal Memory L1P, L1D, L2 Internal PeripheralsExternal Memory Interface Memory Interfaces Overview1 DDR2 External Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsCore Domains OverviewClock Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Voltage Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlSystem PLLC1 Output Clocks Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPllout PLL2 ControlDDR PLLC2 Output Clocks Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Base Address End Address Size PLL and Reset Controller ListPLL and Reset Controller Registers PLL Controller RegistersPeripheral ID Register PID Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 D1END2EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions Goset PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat StableALN3 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN2SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 Obsen Auxen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions ObsenBpon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Obson AuxonSYS3ON SYS2ON SYS1ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Module States Power Domain and Module StatesPower Domain States Module StatesExecuting State Transitions Local ResetPower Domain State Transitions Module State TransitionsPSC Interrupts IcePick Emulation CommandsIcePick Emulation Support in the PSC Interrupt EventsModule State Emulation Events Local Reset Emulation EventsInterrupt Registers PSC Registers Power and Sleep Controller PSC RegistersInterrupt Handling Offset Register DescriptionInterrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Clear Register 1 MERRCR1 Field DescriptionsGOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat State Power Domain Status 0 Register PDSTAT0Pordone POR PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsEmuihbie Emurstie Lrst Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewModule Clock ON/OFF PLL Bypass and Power DownClock Management Module Clock Frequency ScalingDSP Module Clock ON/OFF DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock onDSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Identification Device ConfigurationDevice Boot Configuration Status Pin Multiplexing Control3 DDR2 VTP Control Timer ControlVpss Clock and DAC Control HPI ControlTMS320DM643x DMP Master IDs Bandwidth ManagementBus Master DMA Priority Control DSP CFGTMS320DM643x DMP Default Master Priorities Edma Transfer Controller ConfigurationBoot Control DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.2 Reset10.1 10.3Reset Types Reset PinsDevice Configurations at Reset Type Initiator EffectDSP Module Reset DSP ResetDSP Local Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP
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