Texas Instruments TMS320DM643x manual Steps for Changing PLL2 Frequency

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PLL2 Control

5.3.2 Steps for Changing PLL2 Frequency

The PLLC2 is programmed similarly to the PLLC1. Refer to the appropriate subsection on how to program the PLL2 clocks:

∙If the PLL is powered down (PLLPWRDN bit in PLLCTL is set to 1), follow the full PLL initialization procedure in Section 5.3.2.2 to initialize the PLL.

∙If the PLL is not powered down (PLLPWRDN bit in PLLCTL is cleared to 0), follow the sequence in Section 5.3.2.3 to change the PLL multiplier.

∙If the PLL is already running at a desired multiplier and you only want to change the SYSCLK dividers, follow the sequence in Section 5.3.2.4.

Note that the PLL is powered down after the following device-level global resets:

∙Power-on Reset (POR)

∙Warm Reset (RESET)

∙Max Reset

In addition, note that the PLL2 frequency directly affects the DDR2 memory controller and the VPSS VPBE clock source (if PLLC2 SYSCLK2 is selected as the VPBE clock source). The DDR2 memory controller requires special sequences to be followed before and after you change the PLL2 frequency. You must follow the additional considerations for the DDR2 memory controller in Section 5.3.2.1 in order to not corrupt DDR2 operation.

5.3.2.1DDR2 Considerations When Modifying PLL2 Frequency

Before changing PLL2 and/or PLLC2 frequency, you must take into account the DDR2 memory controller requirements. If the DDR2 memory controller is used in the system, follow the additional steps in this section to change PLL2 and/or PLLC2 frequency without corrupting DDR2 operation.

∙If the DDR2 memory controller is in reset when you desire to change the PLL2 frequency, follow the steps in Section 5.3.2.1.1.

∙If the DDR2 memory controller is already out of reset when you desire to change the PLL2 frequency, follow the steps in Section 5.3.2.1.2.

5.3.2.1.1 PLL2 Frequency Change Steps When DDR2 Memory Controller is In Reset

This section discusses the steps to change the PLL2 frequency when the DDR2 memory controller is in reset. Note that the DDR2 memory controller is in reset after these device-level global resets: power-on reset, warm reset, max reset.

1.Leave the DDR2 memory controller in reset.

2.Program the PLL2 clocks by following the steps in the appropriate section: Section 5.3.2.2, Section 5.3.2.3, or Section 5.3.2.4. (Discussion in Section 5.3.2 explains which is the appropriate subsection).

3.Initialize the DDR2 memory controller. The steps for DDR2 memory controller initialization are found in the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986).

5.3.2.1.2 PLL2 Frequency Change Steps When DDR2 Memory Controller is Out of Reset

This section discusses the steps to change the PLL2 frequency when the DDR2 memory controller is already out of reset.

 

1.

Stop DDR2 memory controller accesses and purge any outstanding requests.

 

 

2.

Put the DDR2 memory in self-refresh mode and stop the DDR2 memory controller clock. The DDR2

 

 

memory controller clock shut down sequence is in the TMS320DM643x DMP DDR2 Memory Controller

 

 

User's Guide (SPRU986).

 

 

3.

Program the PLL2 clocks by following the steps in the appropriate section: Section 5.3.2.2,

 

 

Section 5.3.2.3, or Section 5.3.2.4. (Discussion in Section 5.3.2 explains which is the appropriate

 

 

subsection).

 

 

4.

Re-enable the DDR2 memory controller clock. The DDR2 memory controller clock on sequence is in

 

 

the TMS320DM643x DMP DDR2 Memory Controller User's Guide (SPRU986).

 

44

PLL Controller

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Read This First About This ManualNotational Conventions Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Peripherals Block DiagramIntroduction DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaInterrupt Controller Intc Power-Down Controller PDCInternal Peripherals Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewMemory Map DSP Internal Memory L1P, L1D, L2External Memory Internal PeripheralsMemory Interfaces Overview 1 DDR2 External Memory InterfaceExternal Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsOverview Clock DomainsCore Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Frequency Flexibility Example PLL1 Frequencies and Dividers 27 MHZ Clock InputCore Voltage Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlDevice Clock Generation Steps for Changing PLL1/Core Domain FrequencySystem PLLC1 Output Clocks PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPLL2 Control DDR PLLC2 Output ClocksPllout Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller List PLL and Reset Controller RegistersPLL and Reset Controller Base Address End Address Size PLL Controller RegistersReset Type Status Register Rstype Reset Type Status Register Rstype Field DescriptionsPeripheral ID Register PID Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm PLL Controller Divider 1 Register PLLDIV1PLL Multiplier Control Register Pllm Field Descriptions D1ENPLL Controller Divider 2 Register PLLDIV2 PLL Controller Divider 3 Register PLLDIV3D2EN D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBpden Bypass Divider Register Bpdiv13. Bypass Divider Register Bpdiv Field Descriptions PLL Controller Command Register Pllcmd PLL Controller Status Register PllstatGoset StablePLL Controller Clock Align Control Register Alnctl ALN2 ALN1ALN3 ALN2SYS3 Plldiv Ratio Change Status Register DchangeSYS3 SYS2 SYS1 Clock Enable Control Register Cken 18. Clock Enable Control Register Cken Field DescriptionsObsen Auxen ObsenClock Status Register Ckstat 19. Clock Status Register Ckstat Field DescriptionsBpon Obson AuxonSysclk Status Register Systat 20. Sysclk Status Register Systat Field DescriptionsSYS3ON SYS2ON SYS1ON SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Number Module Name Default Module State MDSTAT.STATE Power Domain and Module TopologyDM643x DMP Default Module Configuration Power Domain and Module States Power Domain StatesModule States Module StatesLocal Reset Power Domain State TransitionsExecuting State Transitions Module State TransitionsIcePick Emulation Commands IcePick Emulation Support in the PSCPSC Interrupts Interrupt EventsModule State Emulation Events Local Reset Emulation EventsInterrupt Registers Power and Sleep Controller PSC Registers Interrupt HandlingPSC Registers Offset Register DescriptionInterrupt Evaluation Register Inteval Field Descriptions Peripheral Revision and Class Information Register PIDInterrupt Evaluation Register Inteval Module Error Pending Register 1 MERRPR1 Module Error Clear Register 1 MERRCR1Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Clear Register 1 MERRCR1 Field DescriptionsGOSTAT0 Power Domain Transition Command Register PtcmdPower Domain Transition Status Register Ptstat Power Domain Status 0 Register PDSTAT0 Pordone PORState PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsModule Control n Register MDCTLn 15. Module Control n Register MDCTLn Field DescriptionsEmuihbie Emurstie Lrst EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewPLL Bypass and Power Down Clock ManagementModule Clock ON/OFF Module Clock Frequency ScalingDSP Sleep Mode Management DSP Sleep ModesDSP Module Clock ON/OFF DSP Module Clock onDSP Module Clock Off 3.3 V I/O Power DownVideo DAC Power Down Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Configuration Device Boot Configuration StatusDevice Identification Pin Multiplexing ControlTimer Control Vpss Clock and DAC Control3 DDR2 VTP Control HPI ControlBandwidth Management Bus Master DMA Priority ControlTMS320DM643x DMP Master IDs DSP CFGEdma Transfer Controller Configuration Boot ControlTMS320DM643x DMP Default Master Priorities DSP DMA DSP CFG EmacSubmit Documentation Feedback Reset 10.110.2 10.3Reset Pins Device Configurations at ResetReset Types Type Initiator EffectDSP Reset DSP Local ResetDSP Module Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Additions/Modifications/Deletions Revision HistoryTable A-1. Document Revision History Rfid Products ApplicationsDSP
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