Texas Instruments TMS320DM643x manual IcePick Emulation Support in the PSC, PSC Interrupts

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IcePick Emulation Support in the PSC

6.5IcePick Emulation Support in the PSC

The PSC supports IcePick commands that allow IcePick aware emulation tools to have some control over the state of power domains and modules. On the DM643x DMP, this IcePick support only applies to the C64x+ CPU (module number 39 in the AlwaysOn power domain 0).

In particular, Table 6-3shows IcePick emulation commands recognized by the PSC, and indicated ones that apply to the C64x+ CPU on the DM643x DMP.

Table 6-3. IcePick Emulation Commands

Power On and

 

 

 

Enable Features

Power On and Enable Descriptions

Reset Features

Reset Descriptions

Inhibit Sleep

Allows emulation to prevent software from

Assert Reset

Allows emulation to assert the

 

transitioning the module out of the enable state.

 

module’s local reset. Applicable

 

Applicable to the DM643x DMP.

 

to the DM643x DMP.

Force Power

Allows emulation to force the power domain into

Wait Reset

Allows emulation to keep local

 

an on state. Not applicable on the DM643x DMP

 

reset asserted for an extended

 

as AlwaysOn power domain is always on.

 

period of time after software

 

 

 

initiates local reset de-assert.

 

 

 

Applicable to the DM643x DMP.

Force Active

Allows emulation to force the module into the

Block Reset

Allows emulation to block

 

enable state. Applicable to the DM643x DMP.

 

software initiated local and

 

 

 

module resets. Applicable to the

 

 

 

DM643x DMP.

Note: When emulation tools remove the above commands, the PSC immediately executes a state transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in MDCTLn, as set by software.

6.6PSC Interrupts

The PSC has an interrupt that is tied to the C64x+ interrupt controller (INTC). This interrupt is named PSCINT in the interrupt map. The PSC interrupt is generated when certain IcePick emulation events occur.

6.6.1 Interrupt Events

The PSC interrupt is generated when any of the following events occur:

∙Module State Emulation Event

∙Module Local Reset Emulation Event

These interrupt events are summarized in Table 6-4and described in more detail in this section.

 

 

Table 6-4. PSC Interrupt Events

Interrupt Enable Bits

 

Control Register

Status Bit

Interrupt Condition

MDCTLn

EMUIHB

Interrupt occurs when the emulation alters the module state.

MDCTLn

EMURST

Interrupt occurs when the emulation alters the module's local reset.

The PSC interrupt events only apply when IcePick emulation alters the state of the module from the user-programmed state in the NEXT bit in MDCTLn. As discussed in Section 6.5, on the DM643x DMP, IcePick support only applies to the C64x+ CPU (module 39), therefore the PSC interrupt condition only applies to module 39.

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Power and Sleep Controller

SPRU978E–March 2008

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Contents Reference Guide Submit Documentation Feedback Contents PLL Controller Command Register Pllcmd Reset Boot ModesList of Figures List of Tables Submit Documentation Feedback Notational Conventions Read This FirstAbout This Manual Related Documentation From Texas InstrumentsTMS320C6000, C6000 are trademarks of Texas Instruments Introduction Block Diagram IntroductionPeripherals DSP Subsystem in TMS320DM643x DMP Components of the DSP SubsystemSubmit Documentation Feedback TMS320C64x+ Megamodule TMS320C64x+ CPU TMS320C64x+ Megamodule Block Diagram Memory Controllers 1 L1P ControllerL1P L1D2 L1D Controller 3 L2 ControllerExternal Memory Controller EMC Internal DMA IdmaPower-Down Controller PDC Internal PeripheralsInterrupt Controller Intc Bandwidth Manager Submit Documentation Feedback System Memory Memory Map Memory Interfaces OverviewExternal Memory Memory MapDSP Internal Memory L1P, L1D, L2 Internal PeripheralsExternal Memory Interface Memory Interfaces Overview1 DDR2 External Memory Interface Asynchronous Emif InterfaceSubmit Documentation Feedback Device Clocking Overview Clock DomainsCore Domains OverviewClock Domains System Clock Modes and Fixed Ratios for Core Clock DomainsOverall Clocking Diagram HeccCore Voltage Core Frequency FlexibilityExample PLL1 Frequencies and Dividers 27 MHZ Clock Input Divider3 DDR2/EMIF Clock Example PLL2 Frequencies Core Voltage =4 I/O Domains Peripheral I/O Domain ClockVideo Processing Back End VPSSCLKCTL.MUXSEL Bit Clocking Mode Description Possible Clocking ModesPLL Controller PLL Module PLL1 ControlSystem PLLC1 Output Clocks Device Clock GenerationSteps for Changing PLL1/Core Domain Frequency PLLC1 Output Clock Used byInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Changing Sysclk Dividers Example 5-1. Calculating Number of Clock Cycles NPllout PLL2 ControlDDR PLLC2 Output Clocks Output Clock Used by2.1 DDR2 Considerations When Modifying PLL2 Frequency Steps for Changing PLL2 FrequencyInitialization to PLL Mode from PLL Power Down Changing PLL Multiplier Example 5-2. Calculating Number of Clock Cycles N PLL and Reset Controller Base Address End Address Size PLL and Reset Controller ListPLL and Reset Controller Registers PLL Controller RegistersPeripheral ID Register PID Reset Type Status Register RstypeReset Type Status Register Rstype Field Descriptions Peripheral ID Register PID Field DescriptionsPLL Control Register Pllctl PLL Control Register Pllctl Field DescriptionsPLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PllmPLL Controller Divider 1 Register PLLDIV1 D1END2EN PLL Controller Divider 2 Register PLLDIV2PLL Controller Divider 3 Register PLLDIV3 D3ENOscillator Divider 1 Register OSCDIV1 OD1ENBypass Divider Register Bpdiv 13. Bypass Divider Register Bpdiv Field DescriptionsBpden Goset PLL Controller Command Register PllcmdPLL Controller Status Register Pllstat StableALN3 PLL Controller Clock Align Control Register AlnctlALN2 ALN1 ALN2Plldiv Ratio Change Status Register Dchange SYS3 SYS2 SYS1SYS3 Obsen Auxen Clock Enable Control Register Cken18. Clock Enable Control Register Cken Field Descriptions ObsenBpon Clock Status Register Ckstat19. Clock Status Register Ckstat Field Descriptions Obson AuxonSYS3ON SYS2ON SYS1ON Sysclk Status Register Systat20. Sysclk Status Register Systat Field Descriptions SYS3ONPower and Sleep Controller Power and Sleep Controller PSC Integration Power Domain and Module Topology DM643x DMP Default Module ConfigurationNumber Module Name Default Module State MDSTAT.STATE Module States Power Domain and Module StatesPower Domain States Module StatesExecuting State Transitions Local ResetPower Domain State Transitions Module State TransitionsPSC Interrupts IcePick Emulation CommandsIcePick Emulation Support in the PSC Interrupt EventsLocal Reset Emulation Events Interrupt RegistersModule State Emulation Events PSC Registers Power and Sleep Controller PSC RegistersInterrupt Handling Offset Register DescriptionPeripheral Revision and Class Information Register PID Interrupt Evaluation Register IntevalInterrupt Evaluation Register Inteval Field Descriptions Module Error Pending Register 1 MERRPR1 Field Descriptions Module Error Pending Register 1 MERRPR1Module Error Clear Register 1 MERRCR1 Module Error Clear Register 1 MERRCR1 Field DescriptionsPower Domain Transition Command Register Ptcmd Power Domain Transition Status Register PtstatGOSTAT0 State Power Domain Status 0 Register PDSTAT0Pordone POR PordonePower Domain Control 0 Register PDCTL0 NextModule Status n Register MDSTATn 14. Module Status n Register MDSTATn Field DescriptionsEmuihbie Emurstie Lrst Module Control n Register MDCTLn15. Module Control n Register MDCTLn Field Descriptions EmuihbieSubmit Documentation Feedback Power Management Power Management Features Description PSC and Pllc OverviewModule Clock ON/OFF PLL Bypass and Power DownClock Management Module Clock Frequency ScalingDSP Module Clock ON/OFF DSP Sleep Mode ManagementDSP Sleep Modes DSP Module Clock on3.3 V I/O Power Down Video DAC Power DownDSP Module Clock Off Submit Documentation Feedback Interrupt Controller Submit Documentation Feedback System Module Device Identification Device ConfigurationDevice Boot Configuration Status Pin Multiplexing Control3 DDR2 VTP Control Timer ControlVpss Clock and DAC Control HPI ControlTMS320DM643x DMP Master IDs Bandwidth ManagementBus Master DMA Priority Control DSP CFGTMS320DM643x DMP Default Master Priorities Edma Transfer Controller ConfigurationBoot Control DSP DMA DSP CFG EmacSubmit Documentation Feedback 10.2 Reset10.1 10.3Reset Types Reset PinsDevice Configurations at Reset Type Initiator EffectDSP Module Reset DSP ResetDSP Local Reset Software Reset Disable SwRstDisableSynchronous Reset SyncReset Boot Modes Submit Documentation Feedback Revision History Table A-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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