Intel MPCMM0002 manual Processor Features Sheet 2, Pbga

MPCMM0002 CMM—Module Components

Table 2.	Processor Features (Sheet 2 of 2)
		PCI Local Bus Specification, Rev. 2.2 compliant
		PCI-X Addendum to the PCI Local Bus Specification, Rev. 1.0a
		64-bit/66 MHz Operation in PCI Mode
	PCI Bus Interface	64-bit/133 MHz Operation in PCI-X Mode
		Support 32-bit PCI Initiators and Targets
		Four Split Read Requests as Initiator
		Eight Split Read Requests as Target
		64-bit Addressing Support
		PC200 Double Data Rate (DDR) SDRAM
		Up to 1 GByte of 64-bit DDR SDRAM (128 MBytes on MPCMM0002)
	Memory Controller	Up to 512 MBytes of 32-bit DDR SDRAM
		Single-bit Error Correction, Multi-bit Support (ECC)
		1024 Byte Posted Memory Write Queue
		40- and 72-bit wide Memory Interface
		2 KByte or 4 KByte Outbound Read Queue
	Address Translation Unit	4 KByte Outbound Write Queue
		4 KByte Inbound Read and Write Queue
		Connects Internal Bus to PCI/PCI-X Bus
		Two Independent Channels Connected to Internal Bus
		Up to 1064 MByte/s Burst Support in PCI-X Mode
	DMA Controller	Up to 1600 MByte/s Burst Support for Internal Bus
		Two 1 KB Queues in Ch-0 and Ch-1
		232 Addressing Range on Internal Bus Interface
		264 Addressing Range on PCI Interface
		Performs XOR on Read Data
	Application Accelerator Unit	Compute Parity Across Local Memory Blocks
		1 KByte/512 Byte Store Queue
		Two Separate I2C Units (one used on MPCMM0002)
	I2C Bus Interface Units	Serial Bus
		Master/Slave Capabilities
		System Management Functions
	SSP Serial Port	Full-duplex Synchronous Serial Interface
		Supports 7.2 KHz to 1.84 MHz Bit Rates
		One Dedicated Global Time Stamp Counter
	Peripheral Performance
		Fourteen Programmable Event Counters
	Monitoring Unit
		Three Control/Status Registers
	Timers	Two Dual-programmable 32-bit Timers
		Watchdog Timer
	544-Ball, Plastic Ball Grid Array
	(PBGA)
	Eight General Purpose I/O Pins

Intel NetStructure® MPCMM0002 Chassis Management Module
Hardware TPS	July 2007
18	Order Number: 309247-004US