Intel MPCMM0002 manual Data Connector Pinouts Matrix Sheet 2

Page 38

Rear Connections—MPCMM0002 CMM

Table 12.

Data Connector Pinouts Matrix (Sheet 2 of 3)

 

 

 

 

 

 

 

 

 

 

 

E

D

C

B

A

 

 

 

 

 

 

 

5

GA3

 

BP_N_SDA_[4]_B

BP_N_SCL_[4]_B

BP_N_SDA_[4]_A

BP_N_SCL_[4]_A

 

 

 

 

 

 

 

6

GA4

 

BP_N_SDA_[5]_B

BP_N_SCL_[5]_B

BP_N_SDA_[5]_A

BP_N_SCL_[5]_A

 

 

 

 

 

 

 

7

GA5

 

BP_N_SDA_[6]_B

BP_N_SCL_[6]_B

BP_N_SDA_[6]_A

BP_N_SCL_[6]_A

 

 

 

 

 

 

 

8

GA6

 

BP_N_SDA_[7]_B

BP_N_SCL_[7]_B

BP_N_SDA_[7]_A

BP_N_SCL_[7]_A

 

 

 

 

 

 

 

9

GA7

 

BP_N_SDA_[8]_B

BP_N_SCL_[8]_B

BP_N_SDA_[8]_A

BP_N_SCL_[8]_A

 

 

 

 

 

 

10

BP_PRES#

BP_N_SDA_[9]_B

BP_N_SCL_[9]_B

BP_N_SDA_[9]_A

BP_N_SCL_[9]_A

 

 

 

 

 

 

11

BP_PRESI#

BP_N_SDA_[10]_B

BP_N_SCL_[10]_B

BP_N_SDA_[10]_A

BP_N_SCL_[10]_A

 

 

 

 

 

 

 

12

BP_HLY#

 

BP_N_SDA_[11]_B

BP_N_SCL_[11]_B

BP_N_SDA_[11]_A

BP_N_SCL_[11]_A

 

 

 

 

 

 

13

BP_HLYI#

BP_N_SDA_[12]_B

BP_N_SCL_[12]_B

BP_N_SDA_[12]_A

BP_N_SCL_[12]_A

 

 

 

 

 

 

 

14

BP_NGO

 

BP_N_SDA_[13]_B

BP_N_SCL_[13]_B

BP_N_SDA_[13]_A

BP_N_SCL_[13]_A

 

 

 

 

 

 

15

BP_NGOI

BP_N_SDA_[14]_B

BP_N_SCL_[14]_B

BP_N_SDA_[14]_A

BP_N_SCL_[14]_A

 

 

 

 

 

 

 

16

BP_AFT1

 

BP_N_SDA_[15]_B

BP_N_SCL_[15]_B

BP_N_SDA_[15]_A

BP_N_SCL_[15]_A

 

 

 

 

 

 

 

17

BP_AFT2

 

BP_N_SDA_[16]_B

BP_N_SCL_[16]_B

BP_N_SDA_[16]_A

BP_N_SCL_[16]_A

 

 

 

 

 

 

18

BP_AFTREF#

BP_CF_SDA_B

BP_CF_SCL_B

BP_CF_SDA_A

BP_CF_SCL_A

 

 

 

 

 

 

19

BP_AFLED1

BP_SH_SDA_B

BP_SH_SCL_B

BP_SH_SDA_A

BP_SH_SCL_A

 

 

 

 

 

 

20

BP_AFLED2

BP_RED_SDA_B

BP_RED_SCL_B

BP_RED_SDA_A

BP_RED_SCL_A

 

 

 

 

 

 

21

BP_AFPRES

BP_RP_SDA_B

BP_RP_SCL_B

BP_RP_SDA_A

BP_RP_SCL_A

 

 

 

 

 

 

22

FRU_VCCA

BP_SP_SDA_B

BP_SP_SCL_B

BP_SP_SDA_A

BP_SP_SCL_A

 

 

 

 

 

 

23

FRU_VCCB

Reserved for future use

GND

GND

GND

 

 

 

 

 

 

 

24

GPIO5

 

GPIO4

GPIO3

GPIO2

GPIO1

 

 

 

 

 

 

 

25

GPIO10

 

GPIO9

GPIO8

GPIO7

GPIO6

 

 

 

 

 

 

 

26

RESV5

 

RESV4

RESV3

RESV2

RESV1

 

 

 

 

 

 

 

27

RESV10

 

RESV9

RESV8

RESV7

RESV6

 

 

 

 

 

 

28

CFG_SCTS

CFG_SRX

CFG_SRTS

CFG_SDTR

CFG_STX

 

 

 

 

 

 

29

CFG_SDSR

BP_CMM_RESETI#

BP_CMM_RESET#

RP_ENET2_LNK#

RP_ENET1_LNK#

 

 

 

 

 

 

30

BP_PWRSW1

BP_FRU0_STATUS0

BP_FRU1_STATUS0

RP_ENET2_ACT#

RP_ENET1_ACT#

 

 

 

 

 

 

31

BP_PWRSW2

BP_FRU0_STATUS1

BP_FRU1_STATUS1

RP_ENET2_SPD#

RP_ENET1_SPD#

 

 

 

 

 

 

 

32

GND

 

GND

GND

GND

GND

 

 

 

 

 

 

33

RP_ENET1_TX1-

RP_ENET1_TX1+

GND

RP_ENET1_TX0-

RP_ENET1_TX0+

 

 

 

 

 

 

 

34

GND

 

GND

GND

GND

GND

 

 

 

 

 

 

35

RP_ENET1_RX1-

RP_ENET1_RX1+

GND

RP_ENET1_RX0-

RP_ENET1_RX0+

 

 

 

 

 

 

 

 

Intel NetStructure® MPCMM0002 Chassis Management Module

July 2007

Hardware TPS

Order Number: 309247-004US

39

Image 38
Contents Hardware Technical Product Specification Intel NetStructure MPCMM0002 Chassis Management ModuleOrder Number 309247-004US Contents 17.4 Figures TablesOrder Number 309247-004US Revision History Date Revision DescriptionDocument Organization Acronym/Term Meaning Acronyms and TermsAcronyms and Terms User Documentation Architecture SpecificationIntroduction Product DefinitionMPCMM0002 CMM-Introduction Installing the CMM Getting StartedQuick Start Block Diagram Module ComponentsCMM Top View Layout Processor Features Sheet 1 Intel 80321 ProcessorProcessor Features Sheet 2 PbgaSerial Port UARTs MemoryEthernet Fpga Watchdog TimerFpga Features Redundancy and Hot Swap CpldRide-Through Support 10 ADM1026 ControllerHot Swap Controller Ipmb Isolation LogicDual Bus Ipmb Isolation Requirements Ipmb Dual Star IsolationFpga Dimensions Mechanical InformationCMM Backing Plate Dimensions CMM Side View Dimensions Front Panel HardwareCoplanar Mating Connectors Rear Connector PlacementMPCMM0002 CMM Rear Connectors Vertical Mating ConnectorsBackplane Considerations CMM PowerDC Power Input Ipmb RoutingVoltage Usage CDM PowerVoltage Max Where Used Monitored By Current Power Switch Filter TrayChassis Component Element Ethernet RoutingChassis Elements Directly Driven by CMM Hardware Rear Connections CMM Connector PinoutsCMM Power Connector Power Connector Pinouts Pin Signal Purpose Pin LengthPin Staging Power Connector Pinouts MatrixPower Connector Receptacle Pin Placement Sheet 1 Order Mating Tail Pin Code LengthRear Connections-MPCMM0002 CMM CMM Data Connector CMM Data ConnectorData Connector Pinouts Sheet 1 Signal Name Count Type Description Pin Name From TableData Connector Pinouts Sheet 2 Data Connector Pinouts Matrix Sheet 1Data Connector Pinouts Matrix Sheet 2 Data Connector Pinouts Matrix Sheet 3 Order Mating Length Tail Length Pin CodeGuide Post CMM RedundancyMPCMM0002 CMM-Rear Connections CDM Management Chassis Data Modules CDMsCDM Overview CDM Health LED StatesCDM Power CDM RedundancyFront Panel Serial Port PinoutsSerial Port RJ-45 Connector Pin Signal DescriptionEthernet Port Pinouts Ethernet Port PinoutsLED Color Status Description Telco Alarm ConnectorEthernet Port LED States Pin Description Cascading the Telco Alarm ConnectorsTelco Alarm Pinout MxxReset Input Alarm Quiet Switch Ganged Telco Alarm Cable Pinouts with CablingLEDs Alarm LEDsLED Symbol Status Description User-Definable LEDs Health LEDHot Swap LED CMM Health LED StatesChassis Ground and Logic Ground Grounding ConsiderationsESD Discharge Protection Module Orientation ThermalsProcessor Heat Sink Module Airflow PathSide-to-Side Air Flow Typical Airflow and Cooling Requirements Airflow RequirementsBoard Resistance Curve Category CMMsMinimum Air Flow Air Temp Rise Thermal SensorsAirflow Guidelines Management Module Specifications Feature SummaryDimensions and Weight Dimensions and Weight12.3 Environmental Characteristics Environmental CharacteristicsReliability Estimate Data Agency CertificationsAssumptions and Notes Reliability Measure Value UnitsGuidelines for Third Party Chassis Vendors High Level DesignO Signals of the CMM Ipmb BusesIpmb Signal Physical Bus Number Physical Bus Number MappingRadial Bus Topologya Gpio Pins Dedicated I/O PinsExample Configurations Interfacing FRUs to the CMMFRUs Based on the ADM1026 Intelligent FRUsNon-Intelligent FRUs with I2C* Support FRU Data Storage for Non-Intelligent Devices Two-Wire Serial Interface BasedNon-Intelligent FRUs without I2C Support Related Documents Temperature Sensors Fronted by the CMMControllers and I/O Ports for Non-Intelligent Devices Related DocumentsWarranty Information Returning a Defective Product RMAFor Asia and Pacific Apac For the AmericasFor Europe, Middle East, and Africa Emea Warranty Information-MPCMM0002 CMM Customer Support Technical Support and Return for Service AssistanceCustomer Support Sales AssistanceMaterial Declaration Data Sheet CertificationsMaterial Declaration Data Sheet Agency Information North America FCC Class aEnglish Safety Instructions English and French-translated belowTaiwan Class a Warning Statement FrenchJapan Vcci Class a Korean Class a Australia, New Zealand Safety Warnings Mesures de Sécurité MPCMM0002 CMM-Safety Warnings Sicherheitshinweise MPCMM0002 CMM-Safety Warnings Norme di Sicurezza MPCMM0002 CMM-Safety Warnings Instrucciones de Seguridad MPCMM0002 CMM-Safety Warnings Chinese Safety Warning MPCMM0002 CMM-Safety Warnings Fpga Working page only. Do not distribute Working page only. Do not distribute Working page only. Do not distribute