Fujitsu MB89202 manuals
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436 pages 5.1 Mb
5 PREFACE7 iiiCopyright 2005-2008 FUJITSU LIMITED All rights reserved 8 READING THIS MANUAL9 CONTENTS15 Main changes in this edition18 1.1 Features of MB89202/F202RA Series20 1.2 MB89202/F202RA Series Product Lineup22 1.3 Differences between Models23 1.4 Block Diagram of MB89202/F202RA SeriesPort 7 Serial function switching Internal bus Figure 1.4-1 shows the block diagram of the MB89202/F202RA series.Block Diagram of MB89202/F202RA Series Figure 1.4-1 Block Diagram of MB89202/F202RA SeriesPort 4 Port 0 Port 5Port 3 Port 6 8 24 1.5 Pin AssignmentFigure 1.5-1 and Figure 1.5-2 show the pin assignment of the MB89202/F202RA series.Pin Assignment of DIP-32P-M06 Figure 1.5-1 Pin Assignment of DIP-32P-M06 25 9Pin Assignment of FPT-34P-M03 Figure 1.5-2 Pin Assignment of FPT-34P-M03 Note: N.C.: Do not use because it is connected internally. 10 26 1.6 Package DimensionsPackage Dimension of DIP-32P-M06 Figure 1.6-1 Package Dimension of DIP-32P-M06 32-pin plastic SH-DIP Lead pitch 1.778 mm Low space 10.16 mm Sealing method Plastic mold 32-pin plastic SH-DIP (DIP-32P-M06) (DIP-32P-M06) 2003 FUJITSU LIMITED D32018S-c-1-1Dimensions in mm (inches). Note: The values in parentheses are reference values 27 11Package Dimension of FPT-34P-M03 Figure 1.6-2 Package Dimension of FPT-34P-M03 (FPT-34P-M03)2003 FUJITSU LIMITED F34003S-c-2-3 28 1.7 Pin Functions Description30 1.8 I/O Circuit Types34 2.1 Precautions on Handling Devices38 3.1 Memory Space39 23Memory Map Figure 3.1-1 Memory Map 40 3.1.1 Specific-purpose Areas42 3.1.2 Location of 16-bit Data on MemoryUpper digits of 16-bit data and stack data are stored in lower addresses on memory. 43 3.2 Dedicated Register45 3.2.1 Condition Code Register (CCR)47 3.2.2 Register Bank Pointer (RP)XXXXXXXX RP CCR -- - X: Undefined 48 3.3 General-Purpose Registers50 3.4 Interrupts52 3.4.1 Interrupt Level Setting Registers (ILR1 to ILR4)53 3.4.2 Steps in the Interrupt Operation55 3.4.3 Multiple Interrupts56 3.4.4 Interrupt Processing Time57 3.4.5 Stack Operation at Interrupt ProcessingThis section describes how values in registers are saved and restored at interrupt processing. 58 3.4.6 Stack Area for Interrupt Processing59 3.5 Reset61 3.5.1 Reset Flag Register (RSFR)The reset flag register (RSFR) allows confirmation of the source for a generated reset.000EHPONR ERST WDOG SFTR XXXX----B R : Read only : Unused 63 3.5.2 External Reset Pin64 3.5.3 Reset OperationOverview of the Reset Operation Figure 3.5-3 Reset Operation Flow 66 3.5.4 State of Each Pin at Reset67 3.6 Clock68 52Figure 3.6-1 Clock Supply Map 69 3.6.1 Clock GeneratorThe clock generator enables oscillation in active mode and disables oscillation in stop mode. 70 3.6.2 Clock ControllerStandby control register (STBC) 72 3.6.3 System Clock Control Register (SYCC)74 3.6.4 Clock ModeThe clock speed is switched by selecting one of four frequency-divided source clocks (gears). 76 3.6.5 Oscillation Stabilization Wait Time78 3.7 Standby Mode (Low-Power Consumption Mode)79 3.7.1 Operations in Standby ModeThis section describes CPU and peripheral function operation in standby mode. 80 3.7.2 Sleep ModeThis section describes sleep mode. 81 3.7.3 Stop ModeThis section describes the stop mode. 82 3.7.4 Standby Control Register (STBC)Standby Control Register (STBC) Figure 3.7-1 Standby Control Register (STBC) 84 3.7.5 Diagram for State Transition in Standby ModeFigure 3.7-2 shows the state transition diagram in standby mode. 86 3.7.6 Notes on Standby Mode88 3.8 Memory Access ModeThe MB89202/F202RA series supports only single-chip mode for access to memory. 92 4.1 Overview of I/O Ports94 4.2 Port 096 4.2.1 Registers of Port 0 (PDR0, DDR0, and PUL0)This section describes the registers associated with port 0. 98 4.2.2 Operations of Port 0 FunctionsThis section describes the operation of port 0. 100 4.3 Port 3102 4.3.1 Registers of Port 3 (PDR3, DDR3, PUL3)This section describes the registers associated with port 3. 104 4.3.2 Operations of Port 3 FunctionsThis section describes the operation of port 3. 106 4.4 Port 4108 4.4.1 Registers of Port 4 (PDR4)This section describes the registers associated with port 4. 109 4.4.2 Operations of Port 4 FunctionsThis section describes the operation of port 4. 110 4.5 Port 5112 4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5)This section describes the registers associated with port 5. 114 4.5.2 Operations of Port 5 FunctionsThis section describes the operation of port 5. 116 4.6 Port 6117 101CHAPTER 4 I/O PORTS Block Diagram of Port 6 Figure 4.6-1 Block Diagram of Port6Pin For MB89202/V201 For MB89F202/F202RA 119 4.6.1 Registers of Port 6 (PDR6, DDR6, PUL6)This section describes the registers associated with port 6. 121 4.6.2 Operations of Port 6 FunctionsThis section describes the operation of port 6. 123 4.7 Port 7125 4.7.1 Registers of Port 7 (PDR7, DDR7, PUL7)This section describes the registers associated with port 7. 127 4.7.2 Operations of Port 7 FunctionsThis section describes the operation of port 7. 129 4.8 Programming Example of I/O PortThis section provides an example of programming with I/O ports. 132 5.1 Overview of Time-base Timer118 CHAPTER 5 TIME-BASE TIMER 134 5.2 Configuration of Time-base TimerBlock Diagram of Time-base Timer Figure 5.2-1 Block Diagram of Time-base Timer 119 CHAPTER 5 TIME-BASE TIMER 135 5.3 Time-base Timer Control Register (TBTC)Time-base Timer Control Register (TBTC) Figure 5.3-1 Time-base Timer Control Register (TBTC) bit7 bit6 bit5 bit4 bit3bit2 bit1 bit0 000A 00---000 R/W R/W R/W R/W R/W 137 5.4 Interrupt of Time-base Timer138 5.5 Operations of Time-base Timer FunctionsThe time-base timer functions as an interval timer or supplies clocks to some peripherals. 140 5.6 Notes on Using Time-base TimerNotes on using the time-base timer are shown below. 141 5.7 Program Example for Time-base TimerProgramming examples for the time-base timer are shown below. 144 6.1 Overview of Watchdog Timer145 6.2 Configuration of Watchdog Timer146 6.3 Watchdog Control Register (WDTC)The watchdog control register (WDTC) activates and clears the watchdog timer.bit7 bit6 bit5 bit4 bit3bit2 bit1 bit0 0009HRESVWTE3WTE2 WTE1WTE0 0---XXXXB R/W R/W R/W R/W R/W 147 6.4 Operations of Watchdog Timer FunctionsThe watchdog timer generates a watchdog reset when the watchdog timer counter overflows. 148 6.5 Notes on Using Watchdog TimerNotes on using the watchdog timer are provided below. 149 6.6 Program Example for Watchdog Timer Programming examples for the watchdog timer are provided below. 151 CHAPTER 7 8-BIT PWM TIMER329 CHAPTER 14 8-BIT SERIAL I/O373 CHAPTER 17 FLASH MEMORY391 APPENDIX
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