Fujitsu F202RA, MB89202 4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5)

96
CHAPTER 4 I/O PORTS
4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5)
This section describes the registers associated with port 5.
■Functions of Port 5 Registers
●Port 5 data register (PDR5)
The PDR5 register indicates the state of pins. For a pin set to function as an output port, the same value
("0" or "1") as held by the output latch can be read from this register. If the pin is set to function as an input
port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, excepting those for bits to be manipulated, do not
change.
●Port 5 data direction register (DDR5)
A bit of the DDR5 register sets the I/O direction of the pin corresponding to the bit.
When the bit of the DDR5 register is set to "1", the pin functions as an output port. When the bit is set to
"0", the pin functions as an input port.
●Setting the output from a peripheral enable
If a peripheral with an output pin is used, set the output enable bit of the peripheral enable.
As it is apparent from the block diagram, the pin in this mode serves output from the peripheral, thereby
superseding its general-purpose port function.
Because the output from the peripheral has priority, the values set on the PDR5 and DDR5 registers for the
output pin used for the peripheral have no significance, regardless of the value output from the peripheral
and the output enabled.
Table 4.5-3 lists the functions of the port 5 registers.