Fujitsu MB89202, F202RA manual Registers PDR7, DDR7, and PUL7 of Port, PDR7, DDR7, PUL7, 108

CHAPTER 4 I/O PORTS

■Block Diagram of Port 7

Figure 4.7-1 Block Diagram of Port 7

	PDR
		Stop mode (SPL = 1)	Pull-up resistor
	PDR read
ata bus	PDR read
d	(when read-modify-write is
al
	performed)
Intern	Output latch	Pch
	PDR write
			Pin
	DDR	Nch
	DDR write	Stop mode (SPL = 1)
	DDR read
	PUL read
	PUL
	PUL write

■Registers PDR7, DDR7, and PUL7 of Port 7

Registers PDR7, DDR7, and PUL7 are associated with port 7.

The bits of these registers correspond to the pins of port 7 in one-to-one correspondence. Table 4.7-2tabulates the correspondence between the pins and the bits of the port 7 registers.

Table 4.7-2 Correspondence between the Pins and the Bits of the Port 7 Registers

Port name	Bits of associated registers and corresponding pins
Port 7	PDR7, DDR7, PUL7	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
	Pin corresponding to bit	-	-	-	-	-	P72	P71	P70

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