Fujitsu F202RA, MB89202 manual Timer 0 Control Register TCR0

CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER

8.4.2Timer 0 Control Register (TCR0)

The timer 0 control register (TCR0) is used to select functions, allow and prohibit operation, control interrupts, and check interrupt states in timer 0 for the 8-bit mode of the 8/16-bit capture timer/counter or in the 16-bit mode. Even if only timer 0 is used in the 8-bit mode, the timer 1 control register (TCR1) must be initialized.

■Timer 0 Control Register (TCR0)

Figure 8.4-3 Timer 0 Control Register (TCR0)

Address	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0	Initial value
001BH	TIF0	TFCR0 T0IEN		CINV	TCS02 TCS01 TCS00			TSTR0 00000000B
	R	R/W	R/W	R/W	R/W	R/W	R/W	R/W

TSTR0 Timer start bit

0The counter operation is stopped.

1The counter is cleared and increment starts.

TCS02	TCS01	TCS00 Clock source selection bits (oscillation: 12.5 MHz)
0	0	0	2tINST [0.64 ∝s]
0	0	1	4tINST [1.28	∝s]
0	1	0	16tINST [5.12	∝s]
0	1	1	64tINST [20.48 ∝s]
1	0	0	128tINST [40.96 ∝s]
1	0	1	256tINST [81.92 ∝s]
1	1	0	512tINST [163.84 ∝s]
1	1	1	External clock

tINST : Instruction cycle (Affected by the clock mode and others.)

CINV	Count clock selection bit
0	The counter is incremented at the falling edge of a selected
	clock source.
1	The counter is incremented at the rising edge of a selected
	clock source.
T0IEN	Interrupt request enable bit

0Interrupt request output is prohibited.

1Interrupt request output is allowed.

TFCR0 Compare match detection flag clear bit

0Not affected (at read, always "0")

1The compare match detection flag is cleared.

TIF0 Compare match detection flag bit

0No compare match has occurred.

1 A compare match occurred.

R/W : Readable/Writable

R : Read only

: Initial value

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