CHAPTER 3 CPU

3.4.2Steps in the Interrupt Operation

When an interrupt request is generated in a peripheral function, the interrupt controller notifies the CPU of its interrupt level. If the CPU can accept an interrupt, the CPU temporarily stops the program that is handling and starts the interrupt processing routine.

Steps in the Interrupt Operation

The steps for processing an interrupt are: occurrence of a source of an interrupt in a peripheral function, designation of the interrupt request flag bit (request F/F), check on the interrupt request enable bit (enable F/F), check on the interrupt level (ILR1, 2, 3, or 4, and CCR: IL1 and IL0), check on another request with the same level, and check on the interrupt enable flag (CCR: I).

Figure 3.4-2 shows the steps in the interrupt operation.

Figure 3.4-2 Steps in the Interrupt Operation

Internal bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PS

I

 

 

IL

 

 

 

 

Operation

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Check

Com-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

parator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MB89202 CPU

 

 

 

 

 

 

Main

 

Interrupt

program

 

processing

 

 

routine

Cancellation

Update of IL

 

 

of a reset

PC and

Request

 

PS saved

 

 

cleared

Initial setting

Level

check

for interrupt

 

Interrupt processing

RAM

 

Enable

 

F/F

AND

Source

 

F/F

 

Peripheral

.

.

.

Level comparator

Interrupt controller

Execution of main

program Occur- rence of interrupt

PC and PS

restored

PC and PS restored

RETI

After a reset, all interrupt requests are prohibited.

Initialize the peripheral functions that generate interrupts using a initialization program for peripheral functions, specify interrupt levels in the interrupt level setting registers (ILR1 to ILR4) concerned, then start up the peripheral functions.

Interrupt levels 1, 2, and 3 can be specified. Level 1 is the highest level, and level 2 is the second highest level. Level 3 prohibits interrupts from the peripheral functions to which it is assigned.

Run the main program. (For a multiple-interrupt, run the interrupt processing routine.)

When a peripheral function generates a source of an interrupt, the interrupt request flag bit for peripheral function (request F/F) is set to "1". If the interrupt request enable bit for a peripheral function is turned on (enable F/F = 1) at that time, an interrupt request is output to the interrupt controller.

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Fujitsu F202RA, MB89202 manual Steps in the Interrupt Operation

F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

The F202RA variant extends the capabilities of the MB89202 by integrating advanced peripheral functions. It includes built-in timers, A/D converters, and serial communication interfaces, which are essential for interfacing with other hardware components or sensors. The availability of these peripherals reduces the need for additional external circuits, thus contributing to a more compact and cost-effective design.

In terms of power management, the MB89202 series employs advanced power-saving technologies. The microcontroller offers various low-power modes, enabling devices to conserve energy during idle times, making it highly suitable for battery-operated applications. This characteristic not only enhances the efficiency of devices but also extends their operational lifespan.

Moreover, the Fujitsu MB89202 series incorporates robust protection features, including watchdog timers and failure detection mechanisms. These safety features ensure reliable operation in critical systems, making them a preferred choice in applications where failure is not an option.

The MB89202 and F202RA microcontrollers also support a range of development tools and environments, including integrated development environments (IDEs) and software libraries, which facilitate rapid application development. With these tools, developers can efficiently prototype, debug, and optimize their applications.

In summary, the Fujitsu MB89202 and F202RA microcontrollers stand out with their efficient performance, extensive memory options, integrated peripherals, and power-saving capabilities, making them ideal for a wide array of embedded applications. Their reliability and robustness further enhance their attractiveness for designers seeking advanced microcontroller solutions.