12.4.4 A/D Enable Register Aden | Fujitsu F202RA, MB89202 specification

CHAPTER 12 A/D CONVERTER

12.4.4A/D Enable Register (ADEN)

The ADEN register is used to select the analog input port that corresponds to different pins. Writing "1" to an appropriate ADEN register bit enables analog input.

■A/D Enable Register (ADEN)

Figure 12.4-5shows the bit configuration of the A/D enable register.

Figure 12.4-5 A/D Enable Register (ADEN)

Address	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0	Initial value
0034H ADE7 ADE6 ADE5 ADE4 ADE3 ADE2							ADE1	ADE0	00000000B
	R/W	R/W	R/W R/W		R/W	R/W	R/W	R/W
				ADE7 to ADE0					A/D input bits
					0	Port input
					1	Analog input
R/W : Readable/Writable
: Initial value

An A/D input port can be used as a general-purpose I/O port.

The ADEN register is used to select the port that corresponds to the analog input.

Set "1" to the corresponding bit in the ADEN register for the port to be used for analog input. This prevents the DC pass when the middle level voltage is applied to the A/D input port.

When this register is to be used as the A/D input port, do not select the bit that indicates use of a pull-up resistor from the pull-up setting register.

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Fujitsu F202RA, MB89202 manual 12.4.4 A/D Enable Register Aden, 5 A/D Enable Register Aden

F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

The F202RA variant extends the capabilities of the MB89202 by integrating advanced peripheral functions. It includes built-in timers, A/D converters, and serial communication interfaces, which are essential for interfacing with other hardware components or sensors. The availability of these peripherals reduces the need for additional external circuits, thus contributing to a more compact and cost-effective design.

In terms of power management, the MB89202 series employs advanced power-saving technologies. The microcontroller offers various low-power modes, enabling devices to conserve energy during idle times, making it highly suitable for battery-operated applications. This characteristic not only enhances the efficiency of devices but also extends their operational lifespan.

Moreover, the Fujitsu MB89202 series incorporates robust protection features, including watchdog timers and failure detection mechanisms. These safety features ensure reliable operation in critical systems, making them a preferred choice in applications where failure is not an option.

The MB89202 and F202RA microcontrollers also support a range of development tools and environments, including integrated development environments (IDEs) and software libraries, which facilitate rapid application development. With these tools, developers can efficiently prototype, debug, and optimize their applications.

In summary, the Fujitsu MB89202 and F202RA microcontrollers stand out with their efficient performance, extensive memory options, integrated peripherals, and power-saving capabilities, making them ideal for a wide array of embedded applications. Their reliability and robustness further enhance their attractiveness for designers seeking advanced microcontroller solutions.

Contents

F2MC-8L Page Fujitsu Limited Page Structure of This Manual Purpose of This Manual and Intended ReaderFujitsu Limited Trademark This appendix shows the I/O map and instructions list This chapter describes the functions and operation of Uart Copyright 2005-2008 Fujitsu Limited All rights reserved Iii Reading this Manual Example notation of multi-use pins P33/EC pin Contents 127 115 205 135161 279 225243 259 347 313339 Appendix a 357375 403 RST Changes For details, refer to main body Xii Chapter Overview Uart Features of MB89202/F202RA SeriesOverview KB Flash with read protection Low-power consumption modes standby modesUp to 26 pins of I/O ports Wild registers Cmos MB89202/F202RA Series Product Lineup1 MB89202/F202RA Series Models MB89201 MB89F202/F202RA MB89V201 Uart Specification2 CPU and Peripheral Functions of MB89202/F202RA Series PWM Current consumption Differences between Models1 Differences between Models Package MB89201 MB89F202/F202RA MB89V202 1 Block Diagram of MB89202/F202RA Series Block Diagram of MB89202/F202RA Series 1 Pin Assignment of DIP-32P-M06 Pin Assignment 2 Pin Assignment of FPT-34P-M03 Pin Assignment of FPT-34P-M03 Package Dimension of DIP-32P-M06 Package Dimensions Package Dimension of FPT-34P-M03 Pin No Circuit Function Name Type Pin Functions DescriptionPin Functions Description 1/2 Pin Functions Description 2/2 Circuit Types 1/2 Remarks I/O Circuit Types Types Circuit Remarks Circuit Types 2/2 Overview Chapter Handling Devices Precautions on Handling Devices Handling Devices Precautions on Handling Devices Product name Operating voltage Step-down circuit Step-down circuit stabilization time Oscillation stabilization wait time 218/FCH Chapter CPU RAM area Memory SpaceCPU Area address 0000H to 007FH Memory Map Address in the vector table Specific-purpose AreasVector Table Area Address FFC0H to Ffffh 1 Vector /2 Fffe H Ffff H Fffb HFffd H Bit Data Storage State in Stack Location of 16-bit Data on MemoryBit Operand Storage State Accumulator a Dedicated RegisterFunctions of the Dedicated Register Program counter PC Stack pointer SP Temporary Accumulator TIndex register Extra-pointer EP Bits for Indicating Arithmetic Operation Results Condition Code Register CCR IL1 IL0 Bits for Controlling Acceptance of Interrupts1 Interrupt Levels Register Bank Pointer RP 4 Configuration of Register Bank Pointer General-Purpose Registers 1 Configuration of Register Bank Features of the General-purpose Registers 1 Interrupt Requests and Interrupt Vectors 1/2 Interrupts 1 Interrupt Requests and Interrupt Vectors 2/2 L01 to LF1 L00 to LF0 Requested interrupt level Priority Interrupt Level Setting Registers ILR1 to ILR4 2 Steps in the Interrupt Operation Steps in the Interrupt Operation CPU Example of multiple interrupts Multiple Interrupts Interrupt handling time Interrupt Processing TimeInterrupt request sample wait time E0H Stack Operation at Interrupt ProcessingStack Operation at the End of Interrupt Processing XXH ROM Ffffh Stack Area for Interrupt Processing0000H 0080H 0280H RAM 1 Reset Sources Reset Power-on reset Reset Sources and Oscillation Stabilization Wait Time 1 Configuration of Reset Flag Register Rsfr Reset Flag Register Rsfr Wdog Bit name DescriptionPonr Erst Function of the External Reset Pin External Reset Pin 3 Reset Operation Flow Reset Operation Influence from a Reset of Contents in RAM Mode FetchState of Reset Waiting for Stabilization of Oscillation States of Pins after the CPU Reads the Mode Data State of Each Pin at Reset 1shows the clock supply map Clock 1 Clock Supply Map For an external clock Clock GeneratorFor a crystal resonator or ceramic resonator Clock Controller 4 Block Diagram of Clock Controller Oscillation stabilization wait time selector OscillatorSystem clock selector Clock controller System Clock Control Register Sycc 5 Configuration of System Clock Control Register Sycc Instruction Cycle tINST Sycc CS1 CPU Clock ModeGears Clock Speed Switching Function 2 Operations in Each Clock Mode Operations in Active Mode Oscillation stabilization wait time during operation Oscillation Stabilization Wait Time Sycc WT1, WT0 Oscillation stabilization wait time at a reset Stop mode Standby Mode Low-Power Consumption ModeSleep mode Sleep Stop SPL=0 SPL=1 Operations in Standby ModeState of pins in standby mode RUN Cancellation of sleep mode Sleep ModeTransition to sleep mode Transition to stop mode Stop Mode 1 Standby Control Register Stbc Standby Control Register Stbc Resv STPSLP SPL 2 State Transition Diagram Diagram for State Transition in Standby Mode State transition Transition conditions 3 Transition to and Cancellation of Clock ModeTransition to and cancellation of standby mode 4 Transition to and Cancellation of Standby Mode Stbc register Mode STPbit7 SLPbit6 Cancellation of Standby Mode by an Interrupt Oscillation Stabilization Wait Time 1 Settings for Mode Data Memory Access ModeMode Data Operations for Selecting Memory Access Mode 2 Operations for Selecting Memory Access CPU Overview of I/O Ports Programming Example of I/O Port Chapter Ports Functions of Ports Overview of I/O PortsO Ports Xxxxb 2 Registers of PortsRegister name Read/Write Address Initial value Xxxxxxxxb Port Pins of Port PDR0, DDR0, PUL0 Block Diagram of PortRegisters PDR0, DDR0, and PUL0 of Port Registers of Port 0 PDR0, DDR0, and PUL0 2 Pull-up Resistor Settings PUL0 Port 0 pull-up setting register PUL0 Operations of Port 0 Functions Operation in stop mode Input and output form Circuit Name Output Type 1 Pins of Port PDR3, DDR3, PUL3 Registers PDR3, DDR3, and PUL3 of Port Port 3 data register PDR3 Setting a port pin to serve external interruptsSetting the output from a peripheral enable Registers of Port 3 PDR3, DDR3, PUL3 Name Read Write Port 3 pull-up setting register PUL3 Operations of Port 3 Functions Operation in mode enabling the output from a peripheralOperation in mode enabling the input to a peripheral P30/UCK/SCK Input Output PDR4, DDR4, OUT4 Registers of Port Functions of Port 4 Registers When being written Read AddressRegisters of Port 4 PDR4 This section describes the registers associated with port Operations of Port 4 Functions Analog input mode setting Pin may serve Type Input Output Pin of PortInput and output Circuit Pin name Function Form PDR5, DDR5, PUL5 Port 5 data direction register DDR5 Registers of Port 5 PDR5, DDR5, PUL5Port 5 data register PDR5 2 Pull-up Setting Register PUL5 Port 5 pull-up setting register PUL5 Operations of Port 5 Functions P50/PWM Input Output Type Serve Pins of Port Peripherals for Input and output form CircuitPin name Function 101 1 Block Diagram of Port6 102 Registers PDR6, DDR6, and PUL6 of PortPDR6, DDR6, PUL6 Port 6 data direction register DDR6 for P60, P61 Registers of Port 6 PDR6, DDR6, PUL6Port 6 data register 104 Port 6 pull-up setting register PUL6 Operations of Port 6 Functions 106 Pin name Function Input and output form Circuit Output Type Pins of Port 108 Registers PDR7, DDR7, and PUL7 of PortPDR7, DDR7, PUL7 Port 7 data direction register DDR7 Registers of Port 7 PDR7, DDR7, PUL7Port 7 data register PDR7 110 Port 7 pull-up setting register PUL7 Operations of Port 7 Functions 112 Programming Example of I/O Port Processing specification 114 Coding example Chapter TIME-BASE Timer 2 Clock Cycles Supplied by Time-base Timer 1/2 Overview of Time-base TimerTIME-BASE Timer 1 Time Intervals for Time-base Timer 117 2 Clock Cycles Supplied by Time-base Timer 2/2 Counter clear circuit Configuration of Time-base TimerTime-base timer counter Interval timer selector 1 Time-base Timer Control Register Tbtc Time-base Timer Control Register Tbtc TBR TbofTbie TBC1, TBC0 Ffec H Ffed H Interrupt of Time-base Timer Operations of Clock Supply Function Operations of Time-base Timer FunctionsOperations of Time-base Timer 123 2 Operations of Time-base Timer Clearing time-base timer Coding examples Program Example for Time-base Timer 126 Popw a Reti Ends END Chapter Watchdog Timer Time-base timer output Oscillation frequency 12.5 MHz Overview of Watchdog TimerWatchdog Timer 1 Watchdog Timer Time Intervals Counter clear control circuit Configuration of Watchdog TimerWatchdog timer counter 1-bit counter Reset control circuit WTE1, WTE0 Watchdog Control Register WdtcWTE3, WTE2 Time intervals of watchdog timer Operations of Watchdog Timer FunctionsActivating watchdog timer Clearing watchdog timer Stopping watchdog timer Program Example for Watchdog Timer 134 Chapter BIT PWM Timer Count clock cycle Interval Square wave output Hz Overview of 8-bit PWM TimerBIT PWM Timer 1 Range of Intervals and Square Wave Output 137 PWM Timer FunctionsInternal clock Output of an 8/16-bit capture timer/counter 138 1 Block Diagram of an 8-bit PWM Timer Configuration of 8-bit PWM Timer PWM generation circuit and PWM output control circuit Count clock selectorBit counter Comparator P50/PWM pin Pin of 8-bit PWM TimerBlock Diagram of the Pin Related to the 8-bit PWM Timer 1 Registers Related to the 8-bit PWM Timer Registers of 8-bit PWM Timer 2 PWM Control Register Cntr PWM Control Register Cntr TIE Bit name FunctionTPE TIR Xxxxxxxxb While the interval timer is operatingPWM Compare Register Comr Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0023H 146 While the PWM timer is operating Interrupt of 8-bit PWM Timer 1 Setting Interval Timer Functions Operations of the Interval Timer Functions 149 2 Operations of an 8-bit PWM Timer 1 Setting 8-bit PWM Timer Functions Operations of the 8-bit PWM Timer Functions 151 States in Each Mode During Operation 153 While interval timer functions are enabled 154 While PWM timer functions are enabled 00 H 01 H 02 H 03 H 04 H This section provides notes on using 8-bit PWM timerError 156 Processing specifications Program Example for PWM Timer 158 Popw Reti Ends 159 Program Example of PWM Timer Functions 160 Chapter BIT Capture TIMER/ Counter 16-BIT Capture TIMER/COUNTER Overview of 8/16-bit Capture Timer/Counter 163 Count clock cycle Interval time Square wave output range Hz 164 3 Interval Time and Square Wave Output Range in 16-bit Mode 165 Counter Function 1 Block Diagram of 8/16-bit Capture Timer/Counter Configuration of 8/16-bit Capture Timer/Counter Count clock selectors 0/1 Timer 0/1 data registers TDR0, TDR1Timer 0/1 control registers TCR0, TCR1 Bit capture timer/counter interrupt P34/TO/INT10 pin Pins of 8/16-bit Capture Timer/CounterP33/EC pin 169 Block Diagram for 8/16-bit Capture Timer/Counter Pins 1 Registers of 8/16-bit Capture Timer/Counter Registers of 8/16-bit Capture Timer/Counter 2 Capture Control Register Tccr Capture Control Register Tccr 172 3 Timer 0 Control Register TCR0 Timer 0 Control Register TCR0 174 TSTR1 Timer 1 Control Register TCR1 TSTR1 TIF1TFCR1 T1IEN Tsel Timer Output Control Register TCR2PEN Bit mode timer Timer 0 Data Register TDR0 179 Bit mode 7 Timer 1 Data Register TDR1 Timer 1 Data Register TDR1 181 Tcpl Capture Data Registers H and L Tcph and TcplBit6 Bit5 Bit4 Bit3 Bit2 Bit1 Tcph Timer 0 interrupt operation in the 8-bit mode 8/16-bit Capture Timer/Counter of InterruptsBit mode Capture mode Timer Timer 0 + timer 184 FFF4 H FFF5 HFFF2 H FFF3 H 1 Setting of Interval Timer Function Timer Explanation of Operations of Interval Timer Functions 186 2 Setting of Interval Timer Function Timer 187 3 Interval Timer Function Operation in 8-bit Mode Timer 188 4 Setting of Interval Timer Function in 16-bit Mode Operation of Counter Functions 1 Setting of Counter Function in 8-bit Mode 190 Detection of the number of events 191 3 Setting of Counter Function in 16-bit Mode 192 4 Counter Function Operation in 16-bit Mode Functions of Operations of Capture Functions 1 Setting of Capture Function in 8-bit Mode Ccmsk Tcmsk 195 2 Capture Mode Operation 196 3 Setting of Capture Function in 16-bit Mode 1 Counter Operation in Standby Mode and at Halfway Stop 8/16-bit Capture Timer/Counter Operation in Each Mode Using only timer 0 in 8-bit mode 10-1 Error Occurring until the Count Operation is Started 199 Program Example for 8/16-bit Capture Timer/Counter 201 Wari Clrb TIF0Popw Xchw Reti Ends END 202 Program Example of Counter Function 203 Xchw IncwCmpw BNE READ16 204 Chapter BIT PPG Timer 12-BIT PPG Timer Overview of 12-bit PPG Timer 207 Bit PPG Function 208 1 Block Diagram of 12-bit PPG Timer Configuration of 12-bit PPG Timer Circuit 210 Bit PPG control registers 1 RCR21 and 2 RCR22Bit PPG control registers 3 RCR23 and 4 RCR24 P37/BZ/PPG pin Pin of 12-bit PPG Timer 212 PUL write Readable and Writable Unused 213 Registers of 12-bit PPG Timer RCK1, RCK0 1 12-bit PPG Control Register 1 RCR21 Bit PPG Control Register 2 RCR22 2 12-bit PPG Control Register 2 RCR22 Bit PPG Control Register 3 RCR23 3 12-bit PPG Control Register 3 RCR23 217 Rcen Bit PPG Control Register 4 RCR24 4 12-bit PPG Control Register 4 RCR24 1 Setting 12-bit PPG Timer Operations of 12-bit PPG Timer Functions 220 2 Operation of 12-bit PPG Timer Setting change during operation This section provides notes on using the 12-bit PPG timerLimitation of H width setting Resolution 2 Error before Count Operation Start 1 Setting Change during 12-bit PPG Timer Operation Program Example for 12-bit PPG Timer 224 Chapter External Interrupt Circuit 1 Edge External Interrupt Circuit 1 Edge Overview of External Interrupt Circuit 1 Block Diagram of External Interrupt Circuit 1 EIC1, EIC2 Configuration of External Interrupt Circuit 228 Edge detecting circuitsExternal interrupt 1 control registers EIC1, EIC2 TCR2PEN=0 Pins of External Interrupt CircuitP35/INT11 and P36/INT12 pins 1 Pins Associated with External Interrupt Circuit PDR 230 1 Registers Associated with External Interrupt Circuit Registers of External Interrupt Circuit 2 External Interrupt Control Register 1 EIC1 External Interrupt Control Register 1 EIC1 233 EIR1EIE1 EIR0 234 EIE0 3 External Interrupt Control Register 2 EIC2 External Interrupt Control Register 2 EIC2 236 EIR2EIE2 Interrupt of External Interrupt Circuit 238 Exercise Caution when Changing Edge Polarity SelectionFFF8H FFF9H IRQ2 Operations of External Interrupt Circuit 1 Setting External Interrupt Circuit 240 2 Operation of External Interrupt 1 INT10 Program Example for External Interrupt Circuit 242 Chapter External Interrupt Circuit 2 Level External Interrupt Circuit 2 Level External interrupt 2 control register EIE2 Interrupt request generating circuit INT26 P00/INT20/AN4 to P03/INT23/AN7P04/INT24 to P07/INT27 INT25 247 248 Register Bit name External interrupt pin EIE2 External interrupt 2 control register Address 2 External Interrupt Circuit 2 Control Register EIE2 External Interrupt 2 Control Register EIE2 251 3 External Interrupt 2 Flag Register EIF2 External Interrupt 2 Flag Register EIF2 ILR3 007DH LA1 bit5 LA0 bit4 EIE2 255 2 Operation of External Interrupt 2 INT20 Intv Dseg ABS Data Segment ORG 0FFE6H Irqa Wari Aden EQUEIE2 EQU EIF2 EQU 257 Pushw a Xchw A,TPopw a Xchw A,T Reti Ends END 258 Chapter Converter D Converter Overview of A/D Converter 1 Block Diagram of the A/D Converter Configuration of A/D Converter Converter Clock selectorAnalog channel selector Sample hold circuit P03/INT23/AN7 to P00/INT20/AN4 and P43/AN3 to P40/AN0 Pins of A/D Converter 264 Block Diagram of the Pins Related to the A/D Converter 1 Registers Related to the A/D Converter Registers of A/D Converter 2 A/D Control Register 1 ADC1 12.4.1 A/D Control Register 1 ADC1 RESV0 ANS2, ANS1, ANS0ADI Admv 3 A/D Control Register 2 ADC2 12.4.2 A/D Control Register 2 ADC2 269 12.4.3 A/D Data Register Addh and Addl When A/D conversion functions are enabled 5 A/D Enable Register Aden 12.4.4 A/D Enable Register Aden Interrupt of A/D Converter Continuous activation Operations of A/D Converter FunctionsSoftware activation 274 Operations of A/D Conversion Functions Input impedance of the analog input This section describes notes on using the A/D converter 276 Conversion timeInput clock of continuous activation Program Example for A/D Converter 278 MOV AddlMOV Addh This chapter describes the functions and operations of Uart Chapter Uart 1 Uart Operating Modes Overview of Uart 281 Serial SwitchChoice of the Transfer Clock Rate 282 Asynchronous transfer mode Synchronous transfer mode 283 Divider for clock Transfer rate bps 1 Block Diagram of Uart Configuration of Uart Transmission control circuit Serial mode control register SMCClock generator Reception control circuit 286 Uart interrupt sources P32/UI/SI Pins of UartP30/UCK/SCK P31/UO/SO 288 Block Diagram of the UART-relating Pins 1shows the UART-relating registers UART-relating Registers Registers of Uart 2 Serial Mode Control Register SMC Serial Mode Control Register SMC SOE SBLSmde Scke 3 Serial Rate Control Register SRC Serial Rate Control Register SRC 293 4 Serial Status and Data Register SSD Serial Status and Data Register SSD 295 296 Receiving Status Serial Input Data Register Sidr When operating mode is 0, 1, orWhen operating mode is Serial Input Data Register Sidr 7 Serial Output Data Register Sodr Serial Output Data Register Sodr 8 Clock Divider Selection Register UPC Clock Divider Selection Register UPC 300 Pren Ssel Serial Switch Register Ssel5 Description of the Serial Switch Register Ssel Bits 302 10 Block Diagram of Serial Switch Register FFF0H FFF1H IRQ6 Interrupt of UartReception Interrupt Uart Interrupt Related Registers and Vector Table Addresses 1 Transferred Data Format Operations of Uart Functions 305 Theory of Operation for Operating Mode 0, 1, 2, 3 Transmission Operations in Operating Mode 0, 1, 2, or Transmission Operations Operating Mode 0, 1, 2, 4 Reception Operations in Operating Mode 0, 1, or Reception Operations Operating Mode 0, 1, or 308 7 Reception Operations in Operating Mode Reception Operations Operating Mode 2 Only 310 Program Example for Uart Program specifications 312 Chapter BIT Serial I/O 1 Shift Clock Cycle and Transfer Rate Serial Function SwitchingOverview of 8-Bit Serial I/O BIT Serial I/O 1 Block Diagram of 8-bit Serial I/O Configuration of 8-Bit Serial I/O Bit serial I/O interrupt Serial mode register SMRShift clock control circuit Shift clock counter P30/UCK/SCK pin Pins of 8-Bit Serial I/OP32/UI/SI pin P31/UO/SO pin 318 Block Diagram for 8-bit Serial I/O Pins Bit Serial I/O Registers Registers of 8-Bit Serial I/O 2 Serial Mode Register SMR Serial Mode Register SMR 321 SiofSioe CKS1, CKS0 322 BDSSST At serial output operation When the serial I/O is in transfer operationSerial Data Register SDR Serial Data Register SDR 1 8-bit Serial I/O Interrupt Register and Vector Table Interrupt of 8-Bit Serial I/OBit Serial I/O Interrupt Register and Vector Table Serial output operation via internal shift clock Operations of Serial Output Functions 326 Serial output operation using external shift clockOperation at Serial Output Completion Operations of Serial Input Functions Serial input operation using internal shift clock 328 Serial input operation using external shift clockOperation at Serial Input Completion Bit serial I/O operation in stop mode 14.8 8-Bit Serial I/O Operation in Each ModeBit serial I/O operation in sleep mode 330 331 When the External Shift Clock is Used 332 Shift clock idle state This section provides notes on using the 8-bit serial I/OError at serial transfer start Malfunction due to noise Example of 8-Bit Serial I/O Connection 335 Bidirectional Serial I/O Operation Program Example for 8-Bit Serial I/O Popw Reti Ends END Program Example for 8-bit Serial InputWari Clrb Siof Pushw MOV 338 Pushw Xchw MOV SDR Chapter Buzzer Output Clock supplier Buzzer output Square wave output at 12.5 MHz Overview of the Buzzer OutputBuzzer Output 1 Output Frequencies Buzzer output selector Configuration of the Buzzer Output BZ pin Block Diagram of the Pin Related to the Buzzer OutputPin of the Buzzer Output 1 Buzzer Register Bzcr Buzzer Register Bzcr 344 1 Functions of Each Bit in Buzzer Register Bzcr Bzcr EQU Program Example for Buzzer Output 346 Chapter Wild Register Function 1 Wild Register Applicable Addresses Overview of the Wild Register FunctionWild Register Applicable Addresses Wild Register Function Control circuit part Configuration of the Wild Register FunctionMemory area part 1 Registers Related to Wild Register Function Registers of the Wild Register Function WRDR0 Data Setting Registers WRDR0 and WRDR11 Functions of Data Setting Register Wrdr Wild register number Register name Function WRARH1 Higher Address Set Registers WRARH0 and WRARH12 Functions of Higher Address Set Register Wrarh WRARH0 WRARL1 Lower Address Set Registers WRARL0 and WRARL13 Functions of Lower Address Set Register Wrarl WRARL0 5 Address Comparison EN Register Wren Address Comparison EN Register Wren Data Test Set Register Wror Test register. Do not access this register 2 Wild Register Addresses List Operations of the Wild Register FunctionsWild Register Addresses List 1 Operation Order of Wild Register Chapter Flash Memory Flash Memory Overview of Flash MemoryWriting to/Erasing Flash Memory Flash Memory Register 1 Flash Memory Control Status Register Fmcs Flash Memory Control Status Register Fmcs 360 Inte Starting the Flash Memory Automatic Algorithm 1 Command Sequence Table State Confirming the Automatic Algorithm Execution State1 Bit Assignments of Hardware Sequence Flags 2 Hardware Sequence Flag Functions Automatic Erasing Data Polling Flag DQ7 Toggle Bit Flag DQ6 Timing Limit Exceeded Flag DQ5 Toggle Bit-2 Flag DQ2 Detailed Explanation of Writing to Erasing Flash Memory Setting The Read/Reset State Writing to the Flash Memory Writing DataSpecifying Addresses 370 1 Example of the Flash Memory Write Procedure Erasing All Data Erasing Chips Behavior under the Flash Security Feature Flash Security FeatureHow to enable the Flash Security Feature How to disable the Flash Security Feature Flash Content Protection Software Reset, Watchdog Timer ResetProgram Access to Flash Memory 374 Appendix Table A-1 Map 1 Appendix a I/O MapAppendix a I/O Map 377 Table A-1 Map 2 378 Table A-1 Map 3 379 Table A-1 Map 4Explanation on read/write Explanation on initial value Appendix B Overview of the Instructions CCR Explanation on the Codes Representing InstructionsTable B-1 Explanation on Codes on Instructions’ List Code Meaning 382 Explanation on the Items of Instructions’ ListTable B-2 Explanation on Items of Instructions’ List Extended Addressing AddressingDirect addressing 384 Index addressingPointer Addressing Table B.1-1 Vector Table Address Corresponding to vct General-purpose Register AddressingImmediate Addressing Vector Addressing 386 Relative AddressingInherent addressing Movw A, PC Special InstructionsJMP @A 388 Mulu aDivu a 389 Xchw A, PC 390 Appendix B Overview of the Instructions Callv #vct RMW Bit Manipulation Instructions Setb and ClrbTable B.3-1 Bus Operation at Bit Manipulation Instructions Code Mnemonic Table B.4-1 List of Transfer Instructions 1 F2MC-8L Instructions List 393 Table B.4-1 List of Transfer Instructions 2 394 Operation InstructionsTable B.4-2 List of Operation Instructions 1 395 Table B.4-2 List of Operation Instructions 2 396 Table B.4-2 List of Operation Instructions 3 397 Branch InstructionsTable B.4-2 List of Operation Instructions 4 Table B.4-3 List Branch Instructions 398 Other InstructionsTable B.4-4 List of Other Instructions Instruction Map of the F Instruction MapInstruction Map Table B.5-1 shows the instruction map of the F2MC-8L Table C-1 Mask Options Appendix C Mask Options Programming Eprom Appendix D Programming Eprom with Evaluation ChipEprom for use P37/BZ/PPG Table E-1 Pin States in Each Operation ModeAppendix E Pin State of the MB89202/F202RA Series Appendix E Pin State of the MB89202/F202RA Series 403 Index follows on the next This is listed in alphabetic order Numerics Aden ADC Cntr BzcrCCR EIE ComrDDR EIC Fmcs F2MC-8L ILR Memory Access Interrupt Enable BitsInterrupt Level Setting Registers Interval Timer OUT PDR P37/BZ/PPG RCR PUL SDR RsfrRST Sodr SidrSMC SMR TDR TbtcTccr TCR Wrdr WdtcWrarh Wrarl 418 CM25-10153-2E Fujitsu Semiconductor Controller Manual