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Fujitsu F202RA manual Pins of A/D Converter, P03/INT23/AN7 to P00/INT20/AN4 and P43/AN3 to P40/AN0

Models: F202RA MB89202

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CHAPTER 12 A/D CONVERTER

12.3Pins of A/D Converter

This section describes the pins related to the A/D converter and shows a block diagram of the pins related to the A/D converter.

■Pins Related to the A/D Converter

The pins related to the A/D converter are P03/INT23/AN7 to P00/INT20/AN4, and P43/AN3 to P40/AN0 pins.

●P03/INT23/AN7 to P00/INT20/AN4 and P43/AN3 to P40/AN0

P03/INT23/AN7 to P00/INT20/AN4, and P43/AN3 to P40/AN0 pins can be used as general-purpose I/O ports (P03 to P00, and P43 to P40) and as analog inputs (AN7 to AN0).

[AN7 to AN0]

When A/D conversion functions are used, input the analog voltage to be converted to these pins. To enable a pin as the analog input, set "1" to the bit that corresponds to the A/D enable register (ADEN), set "0" to the bit that corresponds to the port data direction register (DDR0), and switch the output transistor to OFF, and select one using the bit for selecting an analog input channel (ADC1: ANS0 to ANS2). Even when the A/D converter is used, pins not used as analog inputs can be used as general- purpose I/O ports.

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Fujitsu F202RA, MB89202 manual Pins of A/D Converter, P03/INT23/AN7 to P00/INT20/AN4 and P43/AN3 to P40/AN0

F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

The F202RA variant extends the capabilities of the MB89202 by integrating advanced peripheral functions. It includes built-in timers, A/D converters, and serial communication interfaces, which are essential for interfacing with other hardware components or sensors. The availability of these peripherals reduces the need for additional external circuits, thus contributing to a more compact and cost-effective design.

In terms of power management, the MB89202 series employs advanced power-saving technologies. The microcontroller offers various low-power modes, enabling devices to conserve energy during idle times, making it highly suitable for battery-operated applications. This characteristic not only enhances the efficiency of devices but also extends their operational lifespan.

Moreover, the Fujitsu MB89202 series incorporates robust protection features, including watchdog timers and failure detection mechanisms. These safety features ensure reliable operation in critical systems, making them a preferred choice in applications where failure is not an option.

The MB89202 and F202RA microcontrollers also support a range of development tools and environments, including integrated development environments (IDEs) and software libraries, which facilitate rapid application development. With these tools, developers can efficiently prototype, debug, and optimize their applications.

In summary, the Fujitsu MB89202 and F202RA microcontrollers stand out with their efficient performance, extensive memory options, integrated peripherals, and power-saving capabilities, making them ideal for a wide array of embedded applications. Their reliability and robustness further enhance their attractiveness for designers seeking advanced microcontroller solutions.

Contents

F2MC-8L Page Fujitsu Limited Page Structure of This Manual Purpose of This Manual and Intended ReaderFujitsu Limited TrademarkThis appendix shows the I/O map and instructions list This chapter describes the functions and operation of UartCopyright 2005-2008 Fujitsu Limited All rights reserved Iii Reading this Manual Example notation of multi-use pins P33/EC pinContents 127 115135 161205 279 225243 259313 339347 Appendix a 357375 403RST Changes For details, refer to main bodyXii Chapter Overview Features of MB89202/F202RA Series OverviewUart KB Flash with read protection Low-power consumption modes standby modesUp to 26 pins of I/O ports Wild registersCmos MB89202/F202RA Series Product Lineup1 MB89202/F202RA Series Models MB89201 MB89F202/F202RA MB89V201Uart Specification2 CPU and Peripheral Functions of MB89202/F202RA Series PWMCurrent consumption Differences between Models1 Differences between Models Package MB89201 MB89F202/F202RA MB89V2021 Block Diagram of MB89202/F202RA Series Block Diagram of MB89202/F202RA Series1 Pin Assignment of DIP-32P-M06 Pin Assignment2 Pin Assignment of FPT-34P-M03 Pin Assignment of FPT-34P-M03Package Dimension of DIP-32P-M06 Package DimensionsPackage Dimension of FPT-34P-M03 Pin Functions Description Pin Functions Description 1/2Pin No Circuit Function Name Type Pin Functions Description 2/2 Circuit Types 1/2 Remarks I/O Circuit TypesTypes Circuit Remarks Circuit Types 2/2Overview Chapter Handling Devices Precautions on Handling DevicesHandling Devices Precautions on Handling DevicesProduct name Operating voltage Step-down circuit Step-down circuit stabilization timeOscillation stabilization wait time 218/FCH Chapter CPU RAM area Memory SpaceCPU Area address 0000H to 007FHMemory Map Address in the vector table Specific-purpose AreasVector Table Area Address FFC0H to Ffffh 1 Vector /2Fffb H Fffd HFffe H Ffff H Location of 16-bit Data on Memory Bit Operand Storage StateBit Data Storage State in Stack Accumulator a Dedicated RegisterFunctions of the Dedicated Register Program counter PCStack pointer SP Temporary Accumulator TIndex register Extra-pointer EPBits for Indicating Arithmetic Operation Results Condition Code Register CCRBits for Controlling Acceptance of Interrupts 1 Interrupt LevelsIL1 IL0 Register Bank Pointer RP 4 Configuration of Register Bank PointerGeneral-Purpose Registers 1 Configuration of Register BankFeatures of the General-purpose Registers 1 Interrupt Requests and Interrupt Vectors 1/2 Interrupts1 Interrupt Requests and Interrupt Vectors 2/2 L01 to LF1 L00 to LF0 Requested interrupt level Priority Interrupt Level Setting Registers ILR1 to ILR42 Steps in the Interrupt Operation Steps in the Interrupt OperationCPU Example of multiple interrupts Multiple InterruptsInterrupt Processing Time Interrupt request sample wait timeInterrupt handling time E0H Stack Operation at Interrupt ProcessingStack Operation at the End of Interrupt Processing XXHROM Ffffh Stack Area for Interrupt Processing0000H 0080H 0280H RAM1 Reset Sources ResetPower-on reset Reset Sources and Oscillation Stabilization Wait Time1 Configuration of Reset Flag Register Rsfr Reset Flag Register RsfrWdog Bit name DescriptionPonr ErstFunction of the External Reset Pin External Reset Pin3 Reset Operation Flow Reset OperationMode Fetch State of Reset Waiting for Stabilization of OscillationInfluence from a Reset of Contents in RAM States of Pins after the CPU Reads the Mode Data State of Each Pin at Reset1shows the clock supply map Clock1 Clock Supply Map Clock Generator For a crystal resonator or ceramic resonatorFor an external clock Clock Controller 4 Block Diagram of Clock ControllerOscillation stabilization wait time selector OscillatorSystem clock selector Clock controllerSystem Clock Control Register Sycc 5 Configuration of System Clock Control Register SyccInstruction Cycle tINST Sycc CS1 CPU Clock ModeGears Clock Speed Switching Function 2 Operations in Each Clock ModeOperations in Active Mode Oscillation stabilization wait time during operation Oscillation Stabilization Wait TimeSycc WT1, WT0 Oscillation stabilization wait time at a resetStandby Mode Low-Power Consumption Mode Sleep modeStop mode Sleep Stop SPL=0 SPL=1 Operations in Standby ModeState of pins in standby mode RUNSleep Mode Transition to sleep modeCancellation of sleep mode Transition to stop mode Stop Mode1 Standby Control Register Stbc Standby Control Register StbcResv STPSLP SPL2 State Transition Diagram Diagram for State Transition in Standby ModeState transition Transition conditions 3 Transition to and Cancellation of Clock ModeTransition to and cancellation of standby mode 4 Transition to and Cancellation of Standby ModeStbc register Mode STPbit7 SLPbit6 Cancellation of Standby Mode by an InterruptOscillation Stabilization Wait Time 1 Settings for Mode Data Memory Access ModeMode Data Operations for Selecting Memory Access Mode2 Operations for Selecting Memory Access CPU Overview of I/O Ports Programming Example of I/O Port Chapter PortsOverview of I/O Ports O PortsFunctions of Ports Xxxxb 2 Registers of PortsRegister name Read/Write Address Initial value XxxxxxxxbPort Pins of PortBlock Diagram of Port Registers PDR0, DDR0, and PUL0 of PortPDR0, DDR0, PUL0 Registers of Port 0 PDR0, DDR0, and PUL0 2 Pull-up Resistor Settings PUL0 Port 0 pull-up setting register PUL0Operations of Port 0 Functions Operation in stop mode Input and output form Circuit Name Output Type 1 Pins of PortPDR3, DDR3, PUL3 Registers PDR3, DDR3, and PUL3 of PortPort 3 data register PDR3 Setting a port pin to serve external interruptsSetting the output from a peripheral enable Registers of Port 3 PDR3, DDR3, PUL3Name Read Write Port 3 pull-up setting register PUL3Operation in mode enabling the output from a peripheral Operation in mode enabling the input to a peripheralOperations of Port 3 Functions P30/UCK/SCK Input Output PDR4, DDR4, OUT4 Registers of PortFunctions of Port 4 Registers When being written Read AddressRegisters of Port 4 PDR4 This section describes the registers associated with portOperations of Port 4 Functions Analog input mode settingPin of Port Input and output Circuit Pin name Function FormPin may serve Type Input Output PDR5, DDR5, PUL5 Registers of Port 5 PDR5, DDR5, PUL5 Port 5 data register PDR5Port 5 data direction register DDR5 2 Pull-up Setting Register PUL5 Port 5 pull-up setting register PUL5Operations of Port 5 Functions P50/PWM Pins of Port Peripherals for Input and output form Circuit Pin name FunctionInput Output Type Serve 101 1 Block Diagram of Port6Registers PDR6, DDR6, and PUL6 of Port PDR6, DDR6, PUL6102 Registers of Port 6 PDR6, DDR6, PUL6 Port 6 data registerPort 6 data direction register DDR6 for P60, P61 104 Port 6 pull-up setting register PUL6Operations of Port 6 Functions 106 Pin name Function Input and output form Circuit Output Type Pins of PortRegisters PDR7, DDR7, and PUL7 of Port PDR7, DDR7, PUL7108 Registers of Port 7 PDR7, DDR7, PUL7 Port 7 data register PDR7Port 7 data direction register DDR7 110 Port 7 pull-up setting register PUL7Operations of Port 7 Functions 112 Programming Example of I/O Port Processing specification114 Coding exampleChapter TIME-BASE Timer 2 Clock Cycles Supplied by Time-base Timer 1/2 Overview of Time-base TimerTIME-BASE Timer 1 Time Intervals for Time-base Timer117 2 Clock Cycles Supplied by Time-base Timer 2/2Counter clear circuit Configuration of Time-base TimerTime-base timer counter Interval timer selector1 Time-base Timer Control Register Tbtc Time-base Timer Control Register TbtcTBR TbofTbie TBC1, TBC0Ffec H Ffed H Interrupt of Time-base TimerOperations of Time-base Timer Functions Operations of Time-base TimerOperations of Clock Supply Function 123 2 Operations of Time-base TimerClearing time-base timer Coding examples Program Example for Time-base Timer126 Popw a Reti Ends ENDChapter Watchdog Timer Time-base timer output Oscillation frequency 12.5 MHz Overview of Watchdog TimerWatchdog Timer 1 Watchdog Timer Time IntervalsCounter clear control circuit Configuration of Watchdog TimerWatchdog timer counter 1-bit counter Reset control circuitWatchdog Control Register Wdtc WTE3, WTE2WTE1, WTE0 Time intervals of watchdog timer Operations of Watchdog Timer FunctionsActivating watchdog timer Clearing watchdog timerStopping watchdog timer Program Example for Watchdog Timer 134 Chapter BIT PWM Timer Count clock cycle Interval Square wave output Hz Overview of 8-bit PWM TimerBIT PWM Timer 1 Range of Intervals and Square Wave OutputPWM Timer Functions Internal clock Output of an 8/16-bit capture timer/counter137 138 1 Block Diagram of an 8-bit PWM Timer Configuration of 8-bit PWM TimerPWM generation circuit and PWM output control circuit Count clock selectorBit counter ComparatorPin of 8-bit PWM Timer Block Diagram of the Pin Related to the 8-bit PWM TimerP50/PWM pin 1 Registers Related to the 8-bit PWM Timer Registers of 8-bit PWM Timer2 PWM Control Register Cntr PWM Control Register CntrTIE Bit name FunctionTPE TIRXxxxxxxxb While the interval timer is operatingPWM Compare Register Comr Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0023H146 While the PWM timer is operatingInterrupt of 8-bit PWM Timer 1 Setting Interval Timer Functions Operations of the Interval Timer Functions149 2 Operations of an 8-bit PWM Timer1 Setting 8-bit PWM Timer Functions Operations of the 8-bit PWM Timer Functions151 States in Each Mode During Operation 153 While interval timer functions are enabled154 While PWM timer functions are enabledThis section provides notes on using 8-bit PWM timer Error00 H 01 H 02 H 03 H 04 H 156 Processing specifications Program Example for PWM Timer158 Popw Reti Ends159 Program Example of PWM Timer Functions160 Chapter BIT Capture TIMER/ Counter 16-BIT Capture TIMER/COUNTER Overview of 8/16-bit Capture Timer/Counter163 Count clock cycle Interval time Square wave output range Hz164 3 Interval Time and Square Wave Output Range in 16-bit Mode165 Counter Function1 Block Diagram of 8/16-bit Capture Timer/Counter Configuration of 8/16-bit Capture Timer/CounterCount clock selectors 0/1 Timer 0/1 data registers TDR0, TDR1Timer 0/1 control registers TCR0, TCR1 Bit capture timer/counter interruptPins of 8/16-bit Capture Timer/Counter P33/EC pinP34/TO/INT10 pin 169 Block Diagram for 8/16-bit Capture Timer/Counter Pins1 Registers of 8/16-bit Capture Timer/Counter Registers of 8/16-bit Capture Timer/Counter2 Capture Control Register Tccr Capture Control Register Tccr172 3 Timer 0 Control Register TCR0 Timer 0 Control Register TCR0174 TSTR1 Timer 1 Control Register TCR1TSTR1 TIF1TFCR1 T1IENTimer Output Control Register TCR2 PENTsel Bit mode timer Timer 0 Data Register TDR0179 Bit mode7 Timer 1 Data Register TDR1 Timer 1 Data Register TDR1181 Tcpl Capture Data Registers H and L Tcph and TcplBit6 Bit5 Bit4 Bit3 Bit2 Bit1 Tcph8/16-bit Capture Timer/Counter of Interrupts Bit mode Capture mode Timer Timer 0 + timerTimer 0 interrupt operation in the 8-bit mode FFF4 H FFF5 H FFF2 H FFF3 H184 1 Setting of Interval Timer Function Timer Explanation of Operations of Interval Timer Functions186 2 Setting of Interval Timer Function Timer187 3 Interval Timer Function Operation in 8-bit Mode Timer188 4 Setting of Interval Timer Function in 16-bit ModeOperation of Counter Functions 1 Setting of Counter Function in 8-bit Mode190 Detection of the number of events191 3 Setting of Counter Function in 16-bit Mode192 4 Counter Function Operation in 16-bit ModeFunctions of Operations of Capture Functions 1 Setting of Capture Function in 8-bit ModeCcmsk Tcmsk 195 2 Capture Mode Operation196 3 Setting of Capture Function in 16-bit Mode1 Counter Operation in Standby Mode and at Halfway Stop 8/16-bit Capture Timer/Counter Operation in Each ModeUsing only timer 0 in 8-bit mode 10-1 Error Occurring until the Count Operation is Started199 Program Example for 8/16-bit Capture Timer/Counter Wari Clrb TIF0 Popw Xchw Reti Ends END201 202 Program Example of Counter FunctionXchw Incw Cmpw BNE READ16203 204 Chapter BIT PPG Timer 12-BIT PPG Timer Overview of 12-bit PPG Timer207 Bit PPG Function208 1 Block Diagram of 12-bit PPG Timer Configuration of 12-bit PPG Timer CircuitBit PPG control registers 1 RCR21 and 2 RCR22 Bit PPG control registers 3 RCR23 and 4 RCR24210 P37/BZ/PPG pin Pin of 12-bit PPG Timer212 PUL writeReadable and Writable Unused 213 Registers of 12-bit PPG TimerRCK1, RCK0 1 12-bit PPG Control Register 1 RCR21Bit PPG Control Register 2 RCR22 2 12-bit PPG Control Register 2 RCR22Bit PPG Control Register 3 RCR23 3 12-bit PPG Control Register 3 RCR23217 RcenBit PPG Control Register 4 RCR24 4 12-bit PPG Control Register 4 RCR241 Setting 12-bit PPG Timer Operations of 12-bit PPG Timer Functions220 2 Operation of 12-bit PPG TimerSetting change during operation This section provides notes on using the 12-bit PPG timerLimitation of H width setting Resolution2 Error before Count Operation Start 1 Setting Change during 12-bit PPG Timer OperationProgram Example for 12-bit PPG Timer 224 Chapter External Interrupt Circuit 1 Edge External Interrupt Circuit 1 Edge Overview of External Interrupt Circuit1 Block Diagram of External Interrupt Circuit 1 EIC1, EIC2 Configuration of External Interrupt CircuitEdge detecting circuits External interrupt 1 control registers EIC1, EIC2228 TCR2PEN=0 Pins of External Interrupt CircuitP35/INT11 and P36/INT12 pins 1 Pins Associated with External Interrupt CircuitPDR 2301 Registers Associated with External Interrupt Circuit Registers of External Interrupt Circuit2 External Interrupt Control Register 1 EIC1 External Interrupt Control Register 1 EIC1233 EIR1EIE1 EIR0234 EIE03 External Interrupt Control Register 2 EIC2 External Interrupt Control Register 2 EIC2EIR2 EIE2236 Interrupt of External Interrupt Circuit Exercise Caution when Changing Edge Polarity Selection FFF8H FFF9H IRQ2238 Operations of External Interrupt Circuit 1 Setting External Interrupt Circuit240 2 Operation of External Interrupt 1 INT10Program Example for External Interrupt Circuit 242 Chapter External Interrupt Circuit 2 Level External Interrupt Circuit 2 Level External interrupt 2 control register EIE2 Interrupt request generating circuitINT26 P00/INT20/AN4 to P03/INT23/AN7P04/INT24 to P07/INT27 INT25247 248 Register Bit name External interrupt pinEIE2 External interrupt 2 control register Address 2 External Interrupt Circuit 2 Control Register EIE2 External Interrupt 2 Control Register EIE2251 3 External Interrupt 2 Flag Register EIF2 External Interrupt 2 Flag Register EIF2ILR3 007DH LA1 bit5 LA0 bit4 EIE2 255 2 Operation of External Interrupt 2 INT20Intv Dseg ABS Data Segment ORG 0FFE6H Irqa Wari Aden EQUEIE2 EQU EIF2 EQUPushw a Xchw A,T Popw a Xchw A,T Reti Ends END257 258 Chapter Converter D Converter Overview of A/D Converter1 Block Diagram of the A/D Converter Configuration of A/D ConverterConverter Clock selectorAnalog channel selector Sample hold circuitP03/INT23/AN7 to P00/INT20/AN4 and P43/AN3 to P40/AN0 Pins of A/D Converter264 Block Diagram of the Pins Related to the A/D Converter1 Registers Related to the A/D Converter Registers of A/D Converter2 A/D Control Register 1 ADC1 12.4.1 A/D Control Register 1 ADC1RESV0 ANS2, ANS1, ANS0ADI Admv3 A/D Control Register 2 ADC2 12.4.2 A/D Control Register 2 ADC2269 12.4.3 A/D Data Register Addh and Addl When A/D conversion functions are enabled5 A/D Enable Register Aden 12.4.4 A/D Enable Register AdenInterrupt of A/D Converter Operations of A/D Converter Functions Software activationContinuous activation 274 Operations of A/D Conversion FunctionsInput impedance of the analog input This section describes notes on using the A/D converterConversion time Input clock of continuous activation276 Program Example for A/D Converter MOV Addl MOV Addh278 This chapter describes the functions and operations of Uart Chapter Uart1 Uart Operating Modes Overview of UartSerial Switch Choice of the Transfer Clock Rate281 282 Asynchronous transfer mode Synchronous transfer mode283 Divider for clock Transfer rate bps1 Block Diagram of Uart Configuration of UartTransmission control circuit Serial mode control register SMCClock generator Reception control circuit286 Uart interrupt sourcesP32/UI/SI Pins of UartP30/UCK/SCK P31/UO/SO288 Block Diagram of the UART-relating Pins1shows the UART-relating registers UART-relating Registers Registers of Uart2 Serial Mode Control Register SMC Serial Mode Control Register SMCSOE SBLSmde Scke3 Serial Rate Control Register SRC Serial Rate Control Register SRC293 4 Serial Status and Data Register SSD Serial Status and Data Register SSD295 296 Receiving StatusSerial Input Data Register Sidr When operating mode is 0, 1, orWhen operating mode is Serial Input Data Register Sidr7 Serial Output Data Register Sodr Serial Output Data Register Sodr8 Clock Divider Selection Register UPC Clock Divider Selection Register UPC300 PrenSerial Switch Register Ssel 5 Description of the Serial Switch Register Ssel BitsSsel 302 10 Block Diagram of Serial Switch RegisterFFF0H FFF1H IRQ6 Interrupt of UartReception Interrupt Uart Interrupt Related Registers and Vector Table Addresses1 Transferred Data Format Operations of Uart Functions305 Theory of Operation for Operating Mode 0, 1, 2,3 Transmission Operations in Operating Mode 0, 1, 2, or Transmission Operations Operating Mode 0, 1, 2,4 Reception Operations in Operating Mode 0, 1, or Reception Operations Operating Mode 0, 1, or308 7 Reception Operations in Operating Mode Reception Operations Operating Mode 2 Only310 Program Example for Uart Program specifications312 Chapter BIT Serial I/O 1 Shift Clock Cycle and Transfer Rate Serial Function SwitchingOverview of 8-Bit Serial I/O BIT Serial I/O1 Block Diagram of 8-bit Serial I/O Configuration of 8-Bit Serial I/OBit serial I/O interrupt Serial mode register SMRShift clock control circuit Shift clock counterP30/UCK/SCK pin Pins of 8-Bit Serial I/OP32/UI/SI pin P31/UO/SO pin318 Block Diagram for 8-bit Serial I/O PinsBit Serial I/O Registers Registers of 8-Bit Serial I/O2 Serial Mode Register SMR Serial Mode Register SMR321 SiofSioe CKS1, CKS0BDS SST322 At serial output operation When the serial I/O is in transfer operationSerial Data Register SDR Serial Data Register SDRInterrupt of 8-Bit Serial I/O Bit Serial I/O Interrupt Register and Vector Table1 8-bit Serial I/O Interrupt Register and Vector Table Serial output operation via internal shift clock Operations of Serial Output FunctionsSerial output operation using external shift clock Operation at Serial Output Completion326 Operations of Serial Input Functions Serial input operation using internal shift clockSerial input operation using external shift clock Operation at Serial Input Completion328 14.8 8-Bit Serial I/O Operation in Each Mode Bit serial I/O operation in sleep modeBit serial I/O operation in stop mode 330 331 When the External Shift Clock is Used332 Shift clock idle state This section provides notes on using the 8-bit serial I/OError at serial transfer start Malfunction due to noiseExample of 8-Bit Serial I/O Connection 335 Bidirectional Serial I/O OperationProgram Example for 8-Bit Serial I/O Popw Reti Ends END Program Example for 8-bit Serial InputWari Clrb Siof Pushw MOV338 Pushw Xchw MOV SDRChapter Buzzer Output Clock supplier Buzzer output Square wave output at 12.5 MHz Overview of the Buzzer OutputBuzzer Output 1 Output FrequenciesBuzzer output selector Configuration of the Buzzer OutputBlock Diagram of the Pin Related to the Buzzer Output Pin of the Buzzer OutputBZ pin 1 Buzzer Register Bzcr Buzzer Register Bzcr344 1 Functions of Each Bit in Buzzer Register BzcrBzcr EQU Program Example for Buzzer Output346 Chapter Wild Register Function 1 Wild Register Applicable Addresses Overview of the Wild Register FunctionWild Register Applicable Addresses Wild Register FunctionConfiguration of the Wild Register Function Memory area partControl circuit part 1 Registers Related to Wild Register Function Registers of the Wild Register FunctionWRDR0 Data Setting Registers WRDR0 and WRDR11 Functions of Data Setting Register Wrdr Wild register number Register name FunctionWRARH1 Higher Address Set Registers WRARH0 and WRARH12 Functions of Higher Address Set Register Wrarh WRARH0WRARL1 Lower Address Set Registers WRARL0 and WRARL13 Functions of Lower Address Set Register Wrarl WRARL05 Address Comparison EN Register Wren Address Comparison EN Register WrenData Test Set Register Wror Test register. Do not access this register2 Wild Register Addresses List Operations of the Wild Register FunctionsWild Register Addresses List 1 Operation Order of Wild RegisterChapter Flash Memory Flash Memory Overview of Flash MemoryWriting to/Erasing Flash Memory Flash Memory Register1 Flash Memory Control Status Register Fmcs Flash Memory Control Status Register Fmcs360 InteStarting the Flash Memory Automatic Algorithm 1 Command Sequence TableState Confirming the Automatic Algorithm Execution State1 Bit Assignments of Hardware Sequence Flags 2 Hardware Sequence Flag FunctionsAutomatic Erasing Data Polling Flag DQ7Toggle Bit Flag DQ6 Timing Limit Exceeded Flag DQ5 Toggle Bit-2 Flag DQ2 Detailed Explanation of Writing to Erasing Flash Memory Setting The Read/Reset State Writing Data Specifying AddressesWriting to the Flash Memory 370 1 Example of the Flash Memory Write ProcedureErasing All Data Erasing Chips Behavior under the Flash Security Feature Flash Security FeatureHow to enable the Flash Security Feature How to disable the Flash Security FeatureSoftware Reset, Watchdog Timer Reset Program Access to Flash MemoryFlash Content Protection 374 Appendix Appendix a I/O Map Appendix a I/O MapTable A-1 Map 1 377 Table A-1 Map 2378 Table A-1 Map 3379 Table A-1 Map 4Explanation on read/write Explanation on initial valueAppendix B Overview of the Instructions CCR Explanation on the Codes Representing InstructionsTable B-1 Explanation on Codes on Instructions’ List Code MeaningExplanation on the Items of Instructions’ List Table B-2 Explanation on Items of Instructions’ List382 Addressing Direct addressingExtended Addressing Index addressing Pointer Addressing384 Table B.1-1 Vector Table Address Corresponding to vct General-purpose Register AddressingImmediate Addressing Vector AddressingRelative Addressing Inherent addressing386 Special Instructions JMP @AMovw A, PC Mulu a Divu a388 389 Xchw A, PC390 Appendix B Overview of the Instructions Callv #vctRMW Bit Manipulation Instructions Setb and ClrbTable B.3-1 Bus Operation at Bit Manipulation Instructions Code MnemonicTable B.4-1 List of Transfer Instructions 1 F2MC-8L Instructions List393 Table B.4-1 List of Transfer Instructions 2Operation Instructions Table B.4-2 List of Operation Instructions 1394 395 Table B.4-2 List of Operation Instructions 2396 Table B.4-2 List of Operation Instructions 3397 Branch InstructionsTable B.4-2 List of Operation Instructions 4 Table B.4-3 List Branch InstructionsOther Instructions Table B.4-4 List of Other Instructions398 Instruction Map of the F Instruction MapInstruction Map Table B.5-1 shows the instruction map of the F2MC-8LTable C-1 Mask Options Appendix C Mask OptionsAppendix D Programming Eprom with Evaluation Chip Eprom for useProgramming Eprom P37/BZ/PPG Table E-1 Pin States in Each Operation ModeAppendix E Pin State of the MB89202/F202RA Series Appendix E Pin State of the MB89202/F202RA Series403 Index follows on the next This is listed in alphabetic orderNumerics Aden ADCBzcr CCRCntr EIE ComrDDR EICFmcs F2MC-8LILR Memory Access Interrupt Enable BitsInterrupt Level Setting Registers Interval TimerOUT PDR P37/BZ/PPGRCR PULRsfr RSTSDR Sodr SidrSMC SMRTDR TbtcTccr TCRWrdr WdtcWrarh Wrarl418 CM25-10153-2E Fujitsu Semiconductor Controller Manual