CHAPTER 13 UART

Table 13.4-3 Explanation of Functions of Each Bit in the Serial Status and Data Register (SSD)

 

Bit name

Description

 

 

 

 

 

• This bit indicates the state of serial input data register (SIDR).

 

 

• When this bit is "1", reading the SSD register, then the SIDR register clears RDRF.

bit7

RDRF:

• When this bit and reception interrupt request enable bit (RIE) are "1", the reception

Received data flag bit

interrupt request is output.

 

 

 

• This bit is intended only for read. Writing a value into this bit has no significance

 

 

and does not affect any operation.

 

 

 

 

 

• This bit indicates that the overrun or framing error occurs.

 

 

• When an error occurs (ORFE = 1), no data is transferred from the reception shift

 

 

register to the SIDR register. Therefore, when an error occurs, the RDRF bit is not

 

ORFE:

set. When this bit is "1", reading the SSD register then SIDR register clears the

bit6

Overrun/Framing error

ORFE bit with "0".

 

flag bit

• When this bit and reception interrupt request enable bit (RIE) are "1", the reception

 

 

interrupt request is output.

 

 

• This bit is intended only for read. Writing a value into this bit has no significance

 

 

and does not affect any operation.

 

 

 

 

 

• This bit indicates the state of serial output data register (SODR).

 

TDRE:

• When this bit is "1", reading the SSD register and writing data into the SODR

bit5

Transmitted data flag

register output the data to the serial data output pin (UO).

 

bit

• When this bit and transmission interrupt request enable bit (TIE) are "1", the

 

 

transmission interrupt request is output.

 

 

 

 

TIE:

• This bit enables or disables the transmission interrupt request to the CPU.

bit4

Transmission interrupt

• When this bit and transmission data flag bit (TDRE) are "1", the transmission

 

request enable bit

interrupt request is output.

 

 

 

 

 

• This bit enables or disables the reception interrupt request to the CPU.

 

RIE:

• When this bit and reception data flag bit (RDRF) are "1", the reception interrupt

bit3

Reception interrupt

request is output.

 

request enable bit

• When this bit and error flag bit (ORFE) are "1", the reception interrupt request for

 

 

an error is output.

 

 

 

bit2

Unused bit

• The value read out from this bit is undefined.

• Writing a value into this bit does not affect any operations.

 

 

 

 

 

 

 

• When parity is not used and operating mode is 2 or 3 (the length of data to be

 

TD8/TP:

transmitted/received is 9), this bit is handled as bit8 in the SODR register. When

bit1

Bit-8 transmitting data/

operating mode is not 2 or 3 and parity is not used, this bit is not significant.

 

parity bit

• When parity is used, this bit selects even parity or odd parity for the transmitted

 

 

data.

 

 

 

 

RD8/RP:

• When parity is not used and operating mode is 2 or 3 (the length of data to be

 

transmitted/received is 9), this bit is handled as bit8 in the SIDR register. When

bit0

Bit-8 receiving data/

operating mode is not 2 or 3 and parity is not used, this bit is not significant.

 

parity bit

 

• When parity is used, this bit indicates the parity of received data.

 

 

 

 

 

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Fujitsu F202RA, MB89202 manual 295

F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

The F202RA variant extends the capabilities of the MB89202 by integrating advanced peripheral functions. It includes built-in timers, A/D converters, and serial communication interfaces, which are essential for interfacing with other hardware components or sensors. The availability of these peripherals reduces the need for additional external circuits, thus contributing to a more compact and cost-effective design.

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In summary, the Fujitsu MB89202 and F202RA microcontrollers stand out with their efficient performance, extensive memory options, integrated peripherals, and power-saving capabilities, making them ideal for a wide array of embedded applications. Their reliability and robustness further enhance their attractiveness for designers seeking advanced microcontroller solutions.