Fujitsu MB89202, F202RA manual External Interrupt 2 Flag Register EIF2

CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)

11.4.2External Interrupt 2 Flag Register (EIF2)

The external interrupt 2 flag register (EIF2) is used to hold the interrupt state by flagging an interrupt request flag when a level interrupt is detected and then clearing the flag.

■External Interrupt 2 Flag Register (EIF2)

Figure 11.4-3 External Interrupt 2 Flag Register (EIF2)

Address bit7	bit6	bit5	bit4	bit3 bit2	bit1	bit0
0037H						IF20
						R/W

Initial value

-------0B

R/W : Readable/Writable : Unused

: Initial value

IF20	External interrupt request flag bit
	When being read	When being written
0	No interrupt request	This bit is cleared
	("L" level not detected)
1	Interrupt request is generated	No change in the bit, does not
	("L" level detected)	affect other operations

Table 11.4-3 Explanation of Functions of Each Bit in External Interrupt 2 Flag Register (EIF2)

	Bit name		Function
bit7		• Bit value is undefined when being read.
to	Unused bits
		• The written value does not affect other operations.
bit1
		• When an "L" level signal is input to one of the external
		interrupt pins(INT20	to INT27) for which external
		interrupt inputs are enabled, this bit is set to "1".
	IF20:	• Writing "0" clears this bit, and writing "1" does not change
		this bit state and does not affect other operations.
bit0	External interrupt
		Note:
	request flag bit
		The external interrupt enable bits of the external interrupt 2
		control register (EIE2:IE20 to IE27) may disable external
		interrupt inputs. Interrupt requests continue to be generated
		and issued to the CPU until the IF20 bit is cleared to "0".

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