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CHAPTER 5 TIME-BASE TIMER
5.3 Time-base Timer Control Register (TBTC)

The time-base timer control register (TBTC) selects a time interval, clears the counter,

controls interrupts, or checks the status.

Time-base Timer Control Register (TBTC)
Figure 5.3-1 Time-base Timer Control Register (TBTC)
TBR
0
1
TBC1 TBC0
00 213
/
FCH
01
10
11
TBIE
0
1
TBOF
0
1

bit7 bit6 bit5 bit4 bit3bit2 bit1 bit0

000A

H
TBOF TBIE TBC1 TBC0 TBR

00---000

B

R/W R/W R/W R/W R/W

R/W : Readable/Writable
: Initial value
215
/
FCH
218
/
FCH
222
/
FCH
Address Initial value
Time-base timer initialization bit
Read
ReadWrite
The time-base timer counter is cleared.
Write
"1" is always read. Nothing is changed and affected.
Time interval selection bits
FCH: Oscillation frequency
Interrupt request enable bit
The interrupt request output is disabled.
The interrupt request output is enabled.
Overflow interrupt request flag bit
The specified bit has not overflowed. This bit is cleared.
The specified bit has overflowed. Nothing is changed and affected.
: Unused