Fujitsu MB89202, F202RA manual Setting Change during 12-bit PPG Timer Operation

CHAPTER 9 12-BIT PPG TIMER

Figure 9.6-1 Setting Change during 12-bit PPG Timer Operation

Count by counter
"FFF"H	*1
Cycle period setting
(RCR23,24:SCL0 to SCL11)	*1

"H" width setting

(RCR21,22:HSC0 to HSC11)

Overflow

*2

* 3

"00"H

PPG output pulse waveform

Extend by overflow 1 period

*1:

*2:

*3:

Because the count interval of the operating counter is less than the changed setting, the setting is effective only within the cycle.

Because a cycle period less than the count interval of the operating counter is set, synchronization is not detected and the counter overflows.

Because an "H" width less the count interval of the operating counter is set, synchronization is not detected until the next cycle.

●Error

Because the counter start by program is asynchronous with the count-up start by the selected count clock, an error (a time difference) may occur until detection of synchronization of compare values for the "H" width and for the cycle period with a count by the counter. A major error may shorten the time before the above synchronization to one count clock cycle.

Figure 9.6-2illustrates an error (a time difference) before the count operation start.

Figure 9.6-2 Error before Count Operation Start

Count by counter
0		1	2	3	4
Count clock
1 cycle
Error	Count 0
(time	period
difference)
Counter start

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