Fujitsu MB89202, F202RA manual Serial Mode Register SMR

Shift clock selection bits

CHAPTER 14 8-BIT SERIAL I/O

14.4.1Serial Mode Register (SMR)

The serial mode register (SMR) is used to allow and prohibit 8-bit serial I/O operation, select a shift clock, set a transfer direction, control interrupts, and check interrupt states.

■Serial Mode Register (SMR)

Figure 14.4-2 Serial Mode Register (SMR)

Address 0039H

bit7

SIOF R/W

bit6 bit5

SIOE SCKE R/W R/W

bit4

SOE R/W

bit3				bit2	bit1	bit0		Initial value
CKS1			CKS0		BDS	SST		00000000B
R/W				R/W	R/W	R/W
							Serial I/O transfer start bit
		SST
						At read			At write
				Serial I/O transfer is stopped.					Serial I/O transfer is stopped or
	0
									prohibited.
		1 Serial I/O transfer is in progress. Serial I/O transfer is started or allowed.
		BDS				Transfer direction selection bit

0LSB first (serial I/O transfer starts at the lowest bit.)

1MSB first (serial I/O transfer starts at the highest bit.)

CKS1 CKS0

0	0		2 tINST
0	1	Internal shift clock	8 tINST
1	0		32 tINST

11 External shift clock tINST: Instruction cycle

SOE Serial data output allowance bit

0P31/UO/SO is used as a general-purpose port (P31).

1P31/UO/SO is used as a serial data output pin.

SCK pin Output Output Output Input

SCKE 0 1

SIOE

0

1

SIOF

0

1

Shift clock output allowance bit

P30/UCK/SCK is used as a general-purpose port (P30) or the shift clock input pin (SCK).

P30/UCK/SCK is used as the shift clock output pin.

Interrupt request allowance bit

Interrupt request output is prohibited.

Interrupt request output is allowed.

Interrupt request flag bit

At read	At write
Serial transfer has not	This bit is cleared.
terminated.
Serial transfer has already	Remains unchanged. This bit does not
terminated.	affect other bits.

R/W : Readable and Writable : Initial value

320