Fujitsu F202RA, MB89202 manual Divider for clock Transfer rate bps, 283

CHAPTER 13 UART

Table 13.1-4provides an example of the baud rates selectable when the 8-bit PWM timer is used.

Table 13.1-4 Transfer Cycles and Transfer Rates Selectable for the 8-bit PWM Timer

PWM timer		Asynchronous transfer mode		Synchronous transfer mode
count clock				Divider for
cycle	Divider for clock		Transfer rate (bps)		Transfer rate (bps)
				clock
1tINST	CR=0	16	97656 to 763	2	781k to 6.1k
	CR=1	64	24414 to 191
16tINST	CR=0	16	6103 to 47.8	2	48828 to 381.5
	CR=1	64	1526 to 11.9
64tINST	CR=0	16	1526 to 11.9	2	12207 to 95.4
	CR=1	64	381.5 to 3
8/16-bit capture	CR=0	16	48828 to 381.5	2	391k to 3k
timer/counter
	CR=1	64	12207 to 95.4

tINST: Instruction cycle

The system clock control register (SYCC) selects the maximum clock speed (CS1 and CS0 = 11B, 1 instruction cycle = 4/FCH) in active mode.

Figure 13.1-4shows an example of calculating the baud rate when the PWM timer is selected.

Figure 13.1-4 Example of Calculating the Baud Rate (when the PWM Timer is Selected)

Clock gear selected

64/FCH

1= 16/FCH

Value of baud rate	8/FCH
	4/FCH

Input clock select bit (PWM)

1(P1=0,P0=0)

16(P1=0,P0=1)

64(P1=1,P0=0)

8/16 timer (P1=1,P0=1)

Compare register (COMP)

Value specified in the compare register + 1

CR=0:16 2 CR CR=1:64

The value of the baud rate is determined by the clock input specified in the clock dividing rate register (CS1 and CS0). The clock input is determined with an external clock (PWM timer). For calculation, see Table 13.1-3and Table 13.1-4 .

•When an external clock is selected (FCH = 12.5 MHz) 1/49kbps=1.28 ∝s (min.) ⋅ 16 (CR=0)

•When the PWM timer is selected (FCH = 12.5 MHz)

1/98kbps=0.32 ∝s (4/FCH) ⋅ 1 (P1=0,P0=0) ⋅ 1 (COMR=0) ⋅ 2 ⋅ 16 (CR=0) 1/24414 bps=0.32 ∝s (4/FCH) ⋅ 1 (P1=0,P0=0) ⋅ 1 (COMR=0) ⋅ 2 ⋅ 64 (CR=1)

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