Fujitsu F202RA, MB89202 manual Block Diagram of Port, PDR5, DDR5, PUL5

CHAPTER 4 I/O PORTS

■Block Diagram of Port 5

Figure 4.5-1 Block Diagram of Port 5

Internal data bus

PDR

Stop mode (SPL = 1) Pull-up resistor

PDR read

Output from peripheral Output

enable from peripheral

PDR read

(when read-modify-write is performed)

	Output latch	P-ch
PDR write		Pin
	DDR	N-ch

DDR write

Stop mode (SPL = 1)

DDR read

PUL read

PUL

PUL write

■Registers of Port 5

The registers PDR5, DDR5, and PUL5 are associated with port 5.

One of the bits of these registers corresponds to one pin of port 5.

Table 4.5-2tabulates the correspondence between the pin and a bit of the port 5 registers.

Table 4.5-2 Correspondence between the Pin and a Bit of the Port 5 Registers

Port name	Bits of associated registers and corresponding pins
Port 5	PDR5, DDR5, PUL5	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
	Pin corresponding to bit	-	-	-	-	-	-	-	P50

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