Fujitsu F202RA, MB89202 manual Instruction Cycle tINST, Bit name Description

CHAPTER 3 CPU

Table 3.6-1 Explanation of Functions of Each Bit in the System Clock Control Register (SYCC)

	Bit name	Description
		Used to check the current clock mode.
		When this bit is 0, the clock is stopping or waiting for stabilization of oscillation.
bit7	SCM: System clock	When this bit is 1, operations are performed in active mode.
	monitor bit	Note:
		This bit is read-only enabled. Writing a value to this bit does not affect
		operation.
bit6,	Unused bits	Values in these bits are undefined when read.
bit5		Writing values into these bits does not affect operation.
		Used to select an oscillation stabilization wait time setting.
		When external interrupt causes a return from stop mode to active mode, the
	WT1, WT0:	oscillation stabilization wait time setting selected by these bits is applied.
		The initial values of these bits are determined by options. Therefore, when an
bit4,	Oscillation
		oscillation stabilization wait time setting is to be applied for a reset, it is selected by
bit3	stabilization wait time
		options.
	selection bits
		Note:
		Change values in these bits after confirming that the clock is not waiting for
		stabilization of oscillation using the SCM bit.
		This bit is always "1" when read.
bit2	Unused bit	Note:
		Specify "1".
	CS1, CS0:	Used to select the clock speed in active mode.
bit1,		One of four operating clock speeds (gears) can be specified for the CPU and
	Clock speed selection
bit0		peripheral functions. However, these bits do not affect the operating clock for the
	bits
		time-base timer.

■Instruction Cycle (tINST)

For instruction cycles (minimum instruction run time), a 1/4, 1/8, 1/16, or 1/64 frequency can be selected using the clock speed selection bits (CS1 and CS0).

In active mode, when the oscillation frequency (FCH) is 12.5 MHz, the instruction cycle for the maximum speed (SYCC: CS1 and CS0 = 11B) is 4/FCH (= about 0.32 ∝s).

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