Fujitsu MB89202, F202RA manual Overview of 12-bit PPG Timer, BIT PPG Timer

CHAPTER 9 12-BIT PPG TIMER

9.1Overview of 12-bit PPG Timer

The 12-bit PPG timer is a 12-bit binary counter, enabling the selection of one of four types of internal count clocks. The timer is capable of setting a cycle period and "H" width of output pulse waveforms and can also be used as a remote control transmission frequency generator or 12-bit PPG.

■Functions of 12-bit PPG Timer

•The timer generates a frequency for remote control and outputs signals to a PPG pin.

•The timer is capable of setting a cycle period and "H" width of output pulse waveforms separately.

•The timer enables the selection of a count clock from four types of internal clocks.

•The timer can generate a frequency in a range from twice to 212-1 times as fast as the counter clock. Table 9.1-1lists the ranges in which the output pulse cycle period and "H" width are variable.

Table 9.1-1 Ranges in which the Output Pulse Cycle Period and "H" Width are Variable

Internal count clock	Output pulse cycle period	Output pulse "H" width
cycle period
2tINST	4tINST to 8190tINST	2tINST to 8188tINST
4tINST	8tINST to 16380tINST	4tINST to 16376tINST
16tINST	32tINST to 65520tINST	16tINST to 65504tINST
256tINST	512tINST to 1048.32ktINST	256tINST to 1048.064ktINST

tINST: Instruction cycle (to be affected by a gear function)

Note:

An example of calculating the output pulse cycle period and "H" width as executed by a 12-bit PPG function is given below.

When an oscillation (FCH) of 12.5 MHz and a count clock cycle period of 2 tINST are set, and if:

Compare value for cycle period = 011110B (30-clock period)

Compare value for "H" width = 001010B (10-clock width)

Then, "H" width and the cycle period of output pulse waveforms are calculated as given below. These calculations are obtained provided the system clock control register (SYCC) selects the fastest clock (CS1, CS0 = 11B with one instruction cycle = 4/FCH).

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