CHAPTER 12 A/D CONVERTER

12.5Interrupt of A/D Converter

A factor for an interrupt of the A/D converter is the following.

• Completion of conversion when A/D conversion functions are enabled

Interrupt when A/D Conversion Functions are Enabled

When A/D conversion is completed, the interrupt request flag bit (ADC1: ADI) is set to "1". At this time, if

the bit for enabling an interrupt request is enabled (ADC2: ADIE = 1), an interrupt request to the CPU (IRQ8) occurs. Write "0" to the ADI bit using the routine for interrupt handling to clear the interrupt request.

The ADI bit is set when A/D conversion is completed, irrespective of the value of the ADIE bit.

Note:

When the ADI bit is "1", if the ADIE bit is enabled (changed from "0" to "1"), an interrupt request occurs immediately.

Register and Vector Table Related to the Interrupt of the A/D Converter

Table 12.5-1 Register and Vector Table Related to the Interrupt of the A/D Converter

 

Register to set the interrupt level

Address of the vector table

Interrupt name

 

 

 

 

 

Register

Bit to be set

High order

Low order

 

 

 

 

 

 

 

IRQ8

ILR3 (007DH)

L81 (bit1)

L80 (bit0)

FFEAH

FFEBH

 

 

 

 

 

 

See Section "3.4.2 Steps in the Interrupt Operation " for the interrupt operation.

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Fujitsu MB89202, F202RA manual Interrupt of A/D Converter, IRQ8

F202RA, MB89202 specifications

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