CHAPTER 3 CPU

3.4.4Interrupt Processing Time

From when an interrupt request is generated to when control is transferred to the interrupt processing routine, both the time to quit the instruction being executed and the time to manage the interrupt (required to prepare interrupt processing) are required. The total time must be within 30 instruction cycles.

■Interrupt Processing Time

From when an interrupt request is generated and accepted to when the interrupt processing routine starts, sufficient time is required to wait for an interrupt request sample and to manage the interrupt.

●Interrupt request sample wait time

Generation of an interrupt request is checked by sampling an interrupt request at the last cycle of each instruction. Therefore, the CPU cannot identify an interrupt request while it is executing an instruction. The wait time becomes maximum when an interrupt request is generated immediately after the CPU executes the DIVU instruction (21 instruction cycles) with the longest instruction cycle.

●Interrupt handling time

After accepting an interrupt, the CPU needs 9 instruction cycles for interrupt processing preparation to:

•Save the values in the program counter (PC) and program status (PS)

•Set the address at the beginning of the interrupt processing routine (interrupt vector) into the PC

•Update the interrupt level bits (PS: CCR: IL1 and IL0) in the program status (PS).

Figure 3.4-4shows the interrupt processing time.

Figure 3.4-4 Interrupt Processing Time

CPU performs

Execution of

Interrupt handling

Interrupt processing

general instruction

routine

Interrupt wait

Interrupt request

Interrupt handling time

 

time

sample wait time

(9 instruction cycles)

 

 

Interrupt request is generated

 

: Last instruction in which an interrupt is sampled

 

When an interrupt request is generated immediately after the DIVU instruction having the longest instruction cycle (21 instruction cycles), 30 instruction cycles (21 instructions + 9 instructions) are required for the interrupt processing time. However, if the DIVU instruction and MULU instruction are not used in the program, a maximum of 15 (6 instructions + 9 instructions) instructions are required for the instruction processing time.

An instruction cycle is changed by clock speed switching (gears). For details, see Section "3.6 Clock ".

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Fujitsu MB89202, F202RA manual Interrupt Processing Time, Interrupt request sample wait time, Interrupt handling time
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F202RA, MB89202 specifications

The Fujitsu MB89202 and F202RA microcontrollers are part of the 16-bit microcontroller family, renowned for their robust performance and versatility in a variety of embedded system applications. These devices are tailored for high-efficiency operation across diverse industries, including automotive, consumer electronics, and industrial automation.

One of the main features of the MB89202 is its powerful CPU core, which operates at a clock speed of up to 20 MHz. This enables the microcontroller to perform complex calculations and consumer-grade applications seamlessly. The architecture is designed to handle multiple tasks effectively, making it suitable for real-time operations.

Memory capacity is a vital characteristic of the MB89202, featuring on-chip RAM and ROM configurations. The microcontroller can accommodate different memory variants, providing developers with flexibility in memory allocation based on their application requirements. This adaptability facilitates applications ranging from simple control systems to complex data processing tasks.

The F202RA variant extends the capabilities of the MB89202 by integrating advanced peripheral functions. It includes built-in timers, A/D converters, and serial communication interfaces, which are essential for interfacing with other hardware components or sensors. The availability of these peripherals reduces the need for additional external circuits, thus contributing to a more compact and cost-effective design.

In terms of power management, the MB89202 series employs advanced power-saving technologies. The microcontroller offers various low-power modes, enabling devices to conserve energy during idle times, making it highly suitable for battery-operated applications. This characteristic not only enhances the efficiency of devices but also extends their operational lifespan.

Moreover, the Fujitsu MB89202 series incorporates robust protection features, including watchdog timers and failure detection mechanisms. These safety features ensure reliable operation in critical systems, making them a preferred choice in applications where failure is not an option.

The MB89202 and F202RA microcontrollers also support a range of development tools and environments, including integrated development environments (IDEs) and software libraries, which facilitate rapid application development. With these tools, developers can efficiently prototype, debug, and optimize their applications.

In summary, the Fujitsu MB89202 and F202RA microcontrollers stand out with their efficient performance, extensive memory options, integrated peripherals, and power-saving capabilities, making them ideal for a wide array of embedded applications. Their reliability and robustness further enhance their attractiveness for designers seeking advanced microcontroller solutions.
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