Fujitsu F202RA, MB89202 3.6.4 Clock Mode

58
CHAPTER 3 CPU
3.6.4 Clock Mode
The clock speed is switched by selecting one of four frequency-divided source clocks
(gears).
■Operations in Each Clock Mode
Each clock mode allows transition to a corresponding standby (sleep/stop) mode. For details of standby
mode, see Section "3.7 Standby Mode (Low-Power Consumption Mode) ".
■Gears (Clock Speed Switching Function)
Writing one of 00B to 11B into the clock speed selection bits (SYCC: CS1 and CS0) in the system clock
control register selects one of four clock speeds.
The CPU and peripheral circuits operate using the clock speed selected. However, the gear does not affect
the time-base timer.
Power consumption can be reduced by lowering the clock speed.
Table 3.6-2 Operations in Each Clock Mode
Clock speed
Standby
mode Clock
Operating clock in each block Cause that cancels
standby mode
(excepting reset)
SYCC register
(SYCC: CS1
and CS0) CPU time-base
timer Peripheral function
(1, 1)
High
speed
Low
speed
RUN Generated FCH/4 FCH/2 FCH/4 Interrupt request
Sleep Stopped
Stop Stopped Stopped Stopped External interrupt
(1, 0)
RUN Generated FCH/8 FCH/2 FCH/8 Interrupt request
Sleep Stopped
Stop Stopped Stopped Stopped External interrupt
(0, 1)
RUN Generated FCH/16 FCH/2 FCH/16 Interrupt request
Sleep Stopped
Stop Stopped Stopped Stopped External interrupt
(0, 0)
RUN Generated FCH/64 FCH/2 FCH/64 Interrupt request
Sleep Stopped
Stop Stopped Stopped Stopped External interrupt