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PREFACE
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Copyright 2005-2008 FUJITSU LIMITED All rights reserved
READING THIS MANUAL
CONTENTS
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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ................................................... 161
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ......................................... 225
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) ....................................... 243
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Main changes in this edition
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1.1 Features of MB89202/F202RA Series
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1.2 MB89202/F202RA Series Product Lineup
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1.3 Differences between Models
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1.4 Block Diagram of MB89202/F202RA Series
Port 7
Serial function switching
Internal bus
Figure 1.4-1 shows the block diagram of the MB89202/F202RA series.
1.5 Pin Assignment
Figure 1.5-1 and Figure 1.5-2 show the pin assignment of the MB89202/F202RA series.
Pin Assignment of DIP-32P-M06 Figure 1.5-1 Pin Assignment of DIP-32P-M06
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Pin Assignment of FPT-34P-M03 Figure 1.5-2 Pin Assignment of FPT-34P-M03
Note: N.C.: Do not use because it is connected internally.
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1.6 Package Dimensions
Package Dimension of DIP-32P-M06 Figure 1.6-1 Package Dimension of DIP-32P-M06
32-pin plastic SH-DIP Lead pitch 1.778 mm Low space 10.16 mm Sealing method Plastic mold
32-pin plastic SH-DIP (DIP-32P-M06)
(DIP-32P-M06)
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Package Dimension of FPT-34P-M03 Figure 1.6-2 Package Dimension of FPT-34P-M03
(FPT-34P-M03)
2003 FUJITSU LIMITED F34003S-c-2-3
1.7 Pin Functions Description
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1.8 I/O Circuit Types
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2.1 Precautions on Handling Devices
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3.1 Memory Space
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Memory Map Figure 3.1-1 Memory Map
3.1.1 Specific-purpose Areas
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3.1.2 Location of 16-bit Data on Memory
Upper digits of 16-bit data and stack data are stored in lower addresses on memory.
3.2 Dedicated Register
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3.2.1 Condition Code Register (CCR)
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3.2.2 Register Bank Pointer (RP)
XXXXXXXX
RP CCR
-- -
X: Undefined
3.3 General-Purpose Registers
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3.4 Interrupts
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3.4.1 Interrupt Level Setting Registers (ILR1 to ILR4)
3.4.2 Steps in the Interrupt Operation
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3.4.3 Multiple Interrupts
3.4.4 Interrupt Processing Time
3.4.5 Stack Operation at Interrupt Processing
This section describes how values in registers are saved and restored at interrupt processing.
3.4.6 Stack Area for Interrupt Processing
3.5 Reset
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3.5.1 Reset Flag Register (RSFR)
The reset flag register (RSFR) allows confirmation of the source for a generated reset.
000EHPONR ERST WDOG SFTR XXXX----B
R : Read only : Unused
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3.5.2 External Reset Pin
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3.5.3 Reset Operation
Overview of the Reset Operation Figure 3.5-3 Reset Operation Flow
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3.5.4 State of Each Pin at Reset
3.6 Clock
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Figure 3.6-1 Clock Supply Map
3.6.1 Clock Generator
The clock generator enables oscillation in active mode and disables oscillation in stop mode.
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3.6.2 Clock Controller
Standby control register (STBC)
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3.6.3 System Clock Control Register (SYCC)
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3.6.4 Clock Mode
The clock speed is switched by selecting one of four frequency-divided source clocks (gears).
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3.6.5 Oscillation Stabilization Wait Time
X1
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3.7 Standby Mode (Low-Power Consumption Mode)
3.7.1 Operations in Standby Mode
This section describes CPU and peripheral function operation in standby mode.
3.7.2 Sleep Mode
This section describes sleep mode.
3.7.3 Stop Mode
This section describes the stop mode.
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3.7.4 Standby Control Register (STBC)
Standby Control Register (STBC) Figure 3.7-1 Standby Control Register (STBC)
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3.7.5 Diagram for State Transition in Standby Mode
Figure 3.7-2 shows the state transition diagram in standby mode.
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3.7.6 Notes on Standby Mode
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3.8 Memory Access Mode
The MB89202/F202RA series supports only single-chip mode for access to memory.
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4.1 Overview of I/O Ports
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4.2 Port 0
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4.2.1 Registers of Port 0 (PDR0, DDR0, and PUL0)
This section describes the registers associated with port 0.
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4.2.2 Operations of Port 0 Functions
This section describes the operation of port 0.
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4.3 Port 3
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4.3.1 Registers of Port 3 (PDR3, DDR3, PUL3)
This section describes the registers associated with port 3.
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4.3.2 Operations of Port 3 Functions
This section describes the operation of port 3.
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4.4 Port 4
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4.4.1 Registers of Port 4 (PDR4)
This section describes the registers associated with port 4.
4.4.2 Operations of Port 4 Functions
This section describes the operation of port 4.
4.5 Port 5
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4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5)
This section describes the registers associated with port 5.
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4.5.2 Operations of Port 5 Functions
This section describes the operation of port 5.
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4.6 Port 6
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CHAPTER 4 I/O PORTS Block Diagram of Port 6 Figure 4.6-1 Block Diagram of Port6
Pin
For MB89202/V201
For MB89F202/F202RA
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4.6.1 Registers of Port 6 (PDR6, DDR6, PUL6)
This section describes the registers associated with port 6.
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4.6.2 Operations of Port 6 Functions
This section describes the operation of port 6.
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4.7 Port 7
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4.7.1 Registers of Port 7 (PDR7, DDR7, PUL7)
This section describes the registers associated with port 7.
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4.7.2 Operations of Port 7 Functions
This section describes the operation of port 7.
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4.8 Programming Example of I/O Port
This section provides an example of programming with I/O ports.
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5.1 Overview of Time-base Timer
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CHAPTER 5 TIME-BASE TIMER
5.2 Configuration of Time-base Timer
Block Diagram of Time-base Timer Figure 5.2-1 Block Diagram of Time-base Timer
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CHAPTER 5 TIME-BASE TIMER
5.3 Time-base Timer Control Register (TBTC)
Time-base Timer Control Register (TBTC) Figure 5.3-1 Time-base Timer Control Register (TBTC)
bit7 bit6 bit5 bit4 bit3bit2 bit1 bit0 000A
00---000
R/W R/W R/W R/W R/W
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5.4 Interrupt of Time-base Timer
5.5 Operations of Time-base Timer Functions
The time-base timer functions as an interval timer or supplies clocks to some peripherals.
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5.6 Notes on Using Time-base Timer
Notes on using the time-base timer are shown below.
5.7 Program Example for Time-base Timer
Programming examples for the time-base timer are shown below.
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6.1 Overview of Watchdog Timer
6.2 Configuration of Watchdog Timer
6.3 Watchdog Control Register (WDTC)
The watchdog control register (WDTC) activates and clears the watchdog timer.
bit7 bit6 bit5 bit4 bit3bit2 bit1 bit0 0009HRESVWTE3WTE2 WTE1WTE0 0---XXXXB R/W R/W R/W R/W R/W
6.4 Operations of Watchdog Timer Functions
The watchdog timer generates a watchdog reset when the watchdog timer counter overflows.
6.5 Notes on Using Watchdog Timer
Notes on using the watchdog timer are provided below.
6.6 Program Example for Watchdog Timer
Programming examples for the watchdog timer are provided below.
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CHAPTER 7 8-BIT PWM TIMER
This chapter describes the functions and operations of 8-bit PWM timer.
7.1 Overview of 8-bit PWM Timer
Interval
t
7.2 Configuration of 8-bit PWM Timer
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7.3 Pin of 8-bit PWM Timer
7.4 Registers of 8-bit PWM Timer
This section describes the registers related to the 8-bit PWM timer.
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R/W R/W R/W
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7.4.1 PWM Control Register (CNTR)
PWM Control Register (CNTR) Figure 7.4-2 PWM Control Register (CNTR)
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7.4.2 PWM Compare Register (COMR)
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7.5 Interrupt of 8-bit PWM Timer
7.6 Operations of the Interval Timer Functions
This section describes the operations of the interval timer functions of an 8-bit PWM timer.
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7.7 Operations of the 8-bit PWM Timer Functions
This section describes the operations of the 8-bit PWM timer functions.
CNTR
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7.8 States in Each Mode During Operation
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7.9 Notes on Using 8-bit PWM Timer
This section provides notes on using 8-bit PWM timer.
01H02H03H04H
00
Counter value Count clock One cycle
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7.10 Program Example for PWM Timer
This section describes program examples of an 8-bit PWM timer.
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8.1 Overview of 8/16-bit Capture Timer/Counter
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Internal count clock
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8.2 Configuration of 8/16-bit Capture Timer/Counter
Comparator
Data register "L"
Internal data bus
8-bit mode
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8.3 Pins of 8/16-bit Capture Timer/Counter
This section provides pins of 8/16-bit capture timer/counter and a block diagram for these pins.
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8.4 Registers of 8/16-bit Capture Timer/Counter
This section shows registers of 8/16-bit capture timer/counter.
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8.4.1 Capture Control Register (TCCR)
0019H00000000B
Capture Control Register (TCCR) Figure 8.4-2 Capture Control Register (TCCR)
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8.4.2 Timer 0 Control Register (TCR0)
Timer 0 Control Register (TCR0) Figure 8.4-3 Timer 0 Control Register (TCR0)
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8.4.3 Timer 1 Control Register (TCR1)
Timer 1 Control Register (TCR1) Figure 8.4-4 Timer 1 Control Register (TCR1)
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8.4.4 Timer Output Control Register (TCR2)
8.4.5 Timer 0 Data Register (TDR0)
R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable
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8.4.6 Timer 1 Data Register (TDR1)
R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable
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8.4.7 Capture Data Registers H and L (TCPH and TCPL)
8.5 8/16-bit Capture Timer/Counter of Interrupts
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8.6 Explanation of Operations of Interval Timer Functions
This section describes the interval timer function operation of the 8/16-bit capture timer/ counter.
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Figure 8.6-3 Interval Timer Function Operation in 8-bit Mode (Timer 0)
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8.7 Operation of Counter Functions
This section describes the operation of the 8/16-bit capture timer/counter function.
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Figure 8.7-4 Counter Function Operation in 16-bit Mode
Confirm the validity of the values set in the counter operating in 16-bit mode.
8.8 Functions of Operations of Capture Functions
This section describes the capture function operation of the 8/16-bit capture timer/ counter.
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Figure 8.8-2 Capture Mode Operation
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8.9 8/16-bit Capture Timer/Counter Operation in Each Mode
8.10 Notes on Using 8/16-bit Capture Timer/Counter
This section provides notes on using the 8/16-bit capture timer/counter.
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8.11 Program Example for 8/16-bit Capture Timer/Counter
This section provides program examples of the 8/16-bit capture timer/counter.
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9.1 Overview of 12-bit PPG Timer
=10 2 0.32 s
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9.2 Configuration of 12-bit PPG Timer Circuit
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9.3 Pin of 12-bit PPG Timer
Timer
9.4 Registers of 12-bit PPG Timer
This section describes the registers associated with the 12-bit PPG timer.
9.4.1 12-bit PPG Control Register 1 (RCR21)
R/W : Readable/Writable : Initial value
9.4.2 12-bit PPG Control Register 2 (RCR22)
Readable/Writable
9.4.3 12-bit PPG Control Register 3 (RCR23)
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9.4.4 12-bit PPG Control Register 4 (RCR24)
Cycle period setting bits Compare value for the cycle period of 12-bit PPG outputs : Unused
9.5 Operations of 12-bit PPG Timer Functions
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9.6 Notes on Using 12-bit PPG Timer
This section provides notes on using the 12-bit PPG timer.
Counter start
9.7 Program Example for 12-bit PPG Timer
An example of 12-bit PPG timer programming is given below.
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10.1 Overview of External Interrupt Circuit 1
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10.2 Configuration of External Interrupt Circuit 1
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10.3 Pins of External Interrupt Circuit 1
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Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
Internal data bus
Circuit 1
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10.4 Registers of External Interrupt Circuit 1
This section describes the registers associated with external interrupt circuit 1.
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10.4.1 External Interrupt Control Register 1 (EIC1)
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10.4.2 External Interrupt Control Register 2 (EIC2)
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10.5 Interrupt of External Interrupt Circuit 1
Vector Table
10.6 Operations of External Interrupt Circuit 1
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10.7 Program Example for External Interrupt Circuit 1
An example of programming external interrupt circuit 1 is given below.
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11.1 Overview of External Interrupt Circuit 2
11.2 Configuration of External Interrupt Circuit 2
11.3 Pins of External Interrupt Circuit 2
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Circuit 2
External Interrupt Pins
11.4 Registers of External Interrupt Circuit 2
11.4.1 External Interrupt 2 Control Register (EIE2)
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11.4.2 External Interrupt 2 Flag Register (EIF2)
11.5 Interrupt of External Interrupt Circuit 2
Vector Table
11.6 Operations of External Interrupt Circuit 2
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11.7 Program Example for External Interrupt Circuit 2
An example of programming external interrupt circuit 2 is given below.
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12.1 Overview of A/D Converter
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12.2 Configuration of A/D Converter
Block Diagram of the A/D Converter Figure 12.2-1 Block Diagram of the A/D Converter
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12.3 Pins of A/D Converter
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Internal data bus
Figure 12.3-2 Block Diagram of P43/AN3 to P40/AN0 Pins
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12.4 Registers of A/D Converter
Figure 12.4-1 shows the registers related to the A/D converter.
Registers Related to the A/D Converter Figure 12.4-1 Registers Related to the A/D Converter
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12.4.1 A/D Control Register 1 (ADC1)
A/D Control Register 1 (ADC1) Figure 12.4-2 A/D Control Register 1 (ADC1)
A/D conversion functions are activated.
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12.4.2 A/D Control Register 2 (ADC2)
A/D Control Register 2 (ADC2) Figure 12.4-3 A/D Control Register 2 (ADC2)
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12.4.3 A/D Data Register (ADDH and ADDL)
12.4.4 A/D Enable Register (ADEN)
12.5 Interrupt of A/D Converter
12.6 Operations of A/D Converter Functions
The A/D converter can be activated with software or activated continuously.
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12.7 Notes on Using A/D Converter
This section describes notes on using the A/D converter.
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12.8 Program Example for A/D Converter
This section shows a program example of the 10-bit A/D converter.
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13.1 Overview of UART
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13.2 Configuration of UART
Block Diagram of UART Figure 13.2-1 Block Diagram of UART
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13.3 Pins of UART
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Block Diagram of the UART-relating Pins Figure 13.3-1 Block Diagram of UART-relating Pins
Internal data bus
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13.4 Registers of UART
Figure 13.4-1 shows the UART-relating registers.
UART-relating Registers Figure 13.4-1 UART-relating Registers
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13.4.1 Serial Mode Control Register (SMC)
Serial Mode Control Register (SMC) Figure 13.4-2 Serial Mode Control Register (SMC)
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13.4.2 Serial Rate Control Register (SRC)
Serial Rate Control Register (SRC) Figure 13.4-3 Serial Rate Control Register (SRC)
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13.4.3 Serial Status and Data Register (SSD)
Serial Status and Data Register (SSD) Figure 13.4-4 Serial Status and Data Register (SSD)
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13.4.4 Serial Input Data Register (SIDR)
The serial input data register (SIDR) is for inputting (receiving) serial data.
13.4.5 Serial Output Data Register (SODR)
The serial output data register (SODR) sends out (transmits) serial data.
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13.4.6 Clock Divider Selection Register (UPC)
Clock Divider Selection Register (UPC) Figure 13.4-8 Clock Divider Selection Register (UPC)
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13.4.7 Serial Switch Register (SSEL)
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13.5 Interrupt of UART
13.6 Operations of UART Functions
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13.6.1 Transmission Operations (Operating Mode 0, 1, 2, and 3)
13.6.2 Reception Operations (Operating Mode 0, 1, or 3)
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13.6.3 Reception Operations (Operating Mode 2 Only)
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13.7 Program Example for UART
This section provides program example for UART.
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CHAPTER 14 8-BIT SERIAL I/O
This chapter describes the functions and operation of the 8-bit serial I/O.
14.1 Overview of 8-Bit Serial I/O
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14.2 Configuration of 8-Bit Serial I/O
Block Diagram of 8-bit Serial I/O Figure 14.2-1 Block Diagram of 8-bit Serial I/O
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14.3 Pins of 8-Bit Serial I/O
8-bit serial I/O pins include P32/UI/SI, P31/UO/SO, and P30/UCK/SCK pins.
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14.4 Registers of 8-Bit Serial I/O
Figure 14.4-1 shows 8-bit serial I/O registers.
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14.4.1 Serial Mode Register (SMR)
Serial Mode Register (SMR) Figure 14.4-2 Serial Mode Register (SMR)
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14.4.2 Serial Data Register (SDR)
14.5 Interrupt of 8-Bit Serial I/O
An 8-bit serial I/O interrupt is caused by completion of 8-bit serial data I/O.
14.6 Operations of Serial Output Functions
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14.7 Operations of Serial Input Functions
In the 8-bit serial I/O, 8-bit serial input operation synchronized with a shift clock is possible.
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14.8 8-Bit Serial I/O Operation in Each Mode
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14.9 Notes on Using 8-Bit Serial I/O
This section provides notes on using the 8-bit serial I/O.
14.10 Example of 8-Bit Serial I/O Connection
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Figure 14.10-2 Bidirectional Serial I/O Operation
14.11 Program Example for 8-Bit Serial I/O
This section provides program example for 8-bit serial I/O.
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15.1 Overview of the Buzzer Output
/2
Output frequency = F
= 12.5 MHz/1024 12.21 kHz
15.2 Configuration of the Buzzer Output
15.3 Pin of the Buzzer Output
The pin related to the buzzer output is P37/BZ/PPG.
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CHAPTER 15 BUZZER OUTPUT
15.4 Buzzer Register (BZCR)
Buzzer Register (BZCR) Figure 15.4-1 Buzzer Register (BZCR)
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15.5 Program Example for Buzzer Output
This section shows an program example for buzzer output.
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16.1 Overview of the Wild Register Function
16.2 Configuration of the Wild Register Function
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CHAPTER 16 WILD REGISTER FUNCTION
16.3 Registers of the Wild Register Function
Figure 16.3-1 shows the registers related to the wild register function.
16.3.1 Data Setting Registers (WRDR0 and WRDR1)
16.3.2 Higher Address Set Registers (WRARH0 and WRARH1)
16.3.3 Lower Address Set Registers (WRARL0 and WRARL1)
16.3.4 Address Comparison EN Register (WREN)
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16.4 Operations of the Wild Register Functions
This section describes the operation order of the wild register.
CHAPTER 17 FLASH MEMORY
17.1 Overview of Flash Memory
359
CHAPTER 17 FLASH MEMORY
17.2 Flash Memory Control Status Register (FMCS)
Automatic algorithm Termination timing RDYINT bit RDY bit
17.3 Starting the Flash Memory Automatic Algorithm
17.4 Confirming the Automatic Algorithm Execution State
17.4.1 Data Polling Flag (DQ7)
17.4.2 Toggle Bit Flag (DQ6)
17.4.3 Timing Limit Exceeded Flag (DQ5)
17.4.4 Toggle Bit-2 Flag (DQ2)
17.5 Detailed Explanation of Writing to Erasing Flash Memory
17.5.1 Setting The Read/Reset State
17.5.2 Writing Data
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CHAPTER 17 FLASH MEMORY Figure 17.5-1 Example of the Flash Memory Write Procedure
17.5.3 Erasing All Data (Erasing Chips)
17.6 Flash Security Feature
17.7 Notes on using Flash Memory
This section provides notes on using the MB89F202, especially for flash memory.
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APPENDIX
APPENDIX A I/O Map
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APPENDIX B Overview of the Instructions
This section describes the instructions used for the F2MC-8L.
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B.1 Addressing
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B.2 Special Instructions
This section describes the special instructions other than addressing.
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B.3 Bit Manipulation Instructions (SETB and CLRB)
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APPENDIX B Overview of the Instructions
B.4 F2MC-8L Instructions List
Table B.4-1 to Table B.4-4 list the instructions used by the F2MC-8L.
Transfer Instructions Table B.4-1 List of Transfer Instructions (1 / 2)
393
Table B.4-1 List of Transfer Instructions (2 / 2)
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Table B.4-2 List of Operation Instructions (2 / 4)
396
APPENDIX B Overview of the Instructions
Table B.4-2 List of Operation Instructions (3 / 4)
(A) (AL) (TL)
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Branch Instructions
Table B.4-2 List of Operation Instructions (4 / 4)
Table B.4-3 List of Branch Instructions
if N=1 then PC PC+rel if N=0 then PC PC+rel
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B.5 Instruction Map
Table B.5-1 shows the instruction map of the F2MC-8L.
Instruction Map Table B.5-1 Instruction Map of the F2MC-8L
APPENDIX C Mask Options
Table C-1 lists the mask options of the MB89202/F202RA series.
APPENDIX D Programming EPROM with Evaluation Chip
This section describes how to program EPROM with evaluation chip.
APPENDIX E Pin State of the MB89202/F202RA Series
Table E-1 describes the pin states in each operation mode of the MB89202/F202RA series.
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Index
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