Fujitsu MB89202, F202RA manual Appendix a I/O Map, Table A-1 Map 1

APPENDIX A I/O Map

APPENDIX A I/O Map

For the registers of peripheral functions incorporated in the MB89202/F202RA series, the addresses shown in Table A-1are assigned.

■I/O Map

Table A-1	I/O Map (1 / 4)
Address		Register	Register name	Read/write	Initial value
		abbreviation
0000H		PDR0	Port 0 data register	R/W	XXXXXXXX
0001H		DDR0	Port 0 data direction register	W	00000000
0002H
to			Vacancy
0006H
0007H		SYCC	System clock control register	R/W	1--11100
0008H		STBC	Standby control register	R/W	00010---
0009H		WDTC	Watchdog control register	R/W	0---XXXX
000AH		TBTC	Time-base timer control register	R/W	00---000
000BH			Vacancy
000CH		PDR3	Port 3 data register	R/W	XXXXXXXX
000DH		DDR3	Port 3 data direction register	W	00000000
000EH		RSFR	Reset flag register	R	XXXX----
000FH		PDR4	Port 4 data register	R/W	----XXXX
0010H		DDR4	Port 4 data direction register	R/W	----0000
0011H		OUT4	Port 4 output format register	R/W	----0000
0012H		PDR5	Port 5 data register	R/W	-------X
0013H		DDR5	Port 5 data direction register	R/W	-------0
0014H		RCR21	12-bit PPG control register 1	R/W	00000000
0015H		RCR22	12-bit PPG control register 2	R/W	--000000
0016H		RCR23	12-bit PPG control register 3	R/W	0-000000
0017H		RCR24	12-bit PPG control register 4	R/W	--000000

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