Fujitsu F202RA, MB89202 APPENDIX A I/O Map

376
APPENDIX A I/O Map
APPENDIX A I/O Map
For the registers of peripheral functions incorporated in the MB89202/F202RA series,
the addresses shown in Table A-1 are assigned.
■I/O Map
Table A-1 I/O Map (1 / 4)
Address Register
abbreviation Register name Read/write Initial value
0000HPDR0 Port 0 data register R/W XXXXXXXX
0001HDDR0 Port 0 data direction register W 00000000
0002H
to
0006H
Vacancy
0007HSYCC System clock control register R/W 1--11100
0008HSTBC Standby control register R/W 00010---
0009HWDTC Watchdog control register R/W 0---XXXX
000AHTBTC Time-base timer control register R/W 00---000
000BHVacancy
000CHPDR3 Port 3 data register R/W XXXXXXXX
000DHDDR3 Port 3 data direction register W 00000000
000EHRSFR Reset flag register R XXXX----
000FHPDR4 Port 4 data register R/W ----XXXX
0010HDDR4 Port 4 data direction register R/W ----0000
0011HOUT4 Port 4 output format register R/W ----0000
0012HPDR5 Port 5 data register R/W -------X
0013HDDR5 Port 5 data direction register R/W -------0
0014HRCR21 12-bit PPG control register 1 R/W 00000000
0015HRCR22 12-bit PPG control register 2 R/W --000000
0016HRCR23 12-bit PPG control register 3 R/W 0-000000
0017HRCR24 12-bit PPG control register 4 R/W --000000